Commit Graph

61 Commits

Author SHA1 Message Date
Alkis Evlogimenos
39354c99a1 Change MRegisterInfo::foldMemoryOperand to return the folded
instruction to make the API more flexible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12386 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-14 07:19:51 +00:00
Alkis Evlogimenos
71e353ed35 Uncomment assertions that register# != 0 on calls to
MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes
to relevant files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11882 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-26 22:00:20 +00:00
Chris Lattner
7b1af15612 No need to clear the map here, it will always be empty
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11868 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-26 05:21:21 +00:00
Alkis Evlogimenos
4d0d864be3 Add DenseMap template and actually use it for for mapping virtual regs
to objects.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11840 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-25 21:55:45 +00:00
Alkis Evlogimenos
743d0a1f83 Refactor rewinding code for finding the first terminator of a basic
block into MachineBasicBlock::getFirstTerminator().

This also fixes a bug in the implementation of the above in both
RegAllocLocal and InstrSched, where instructions where added after the
terminator if the basic block's only instruction was a terminator (it
shouldn't matter for RegAllocLocal since this case never occurs in
practice).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11748 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-23 18:14:48 +00:00
Chris Lattner
d0d1c8f830 Another bug fix for empty MBB's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11716 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-22 19:37:31 +00:00
Chris Lattner
688c8252d2 Fix a bug where we were implicitly assuming that there would be at least
one terminator instruction in each basic block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11714 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-22 19:08:15 +00:00
Alkis Evlogimenos
d6f6d1a80d Make 'fold' statistic's description the same in both allocators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11687 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-21 18:07:33 +00:00
Chris Lattner
d368c6163a Fix problem fusing spill code into instructions: we didn't update the live
variable information to take into account the change of instruction
address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11628 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-19 18:34:02 +00:00
Alkis Evlogimenos
2acef2da06 Rename reloads/spills to loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11619 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-19 06:19:09 +00:00
Chris Lattner
56ddada278 Remove the -disable-kill option. The register allocator is buggy with it,
and it was only for debugging in the first place.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11557 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 17:49:10 +00:00
Chris Lattner
11390e76e7 Add support to the local allocator for fusing spill code into the instructions
that need them.  This is very useful on CISCy targets like the X86 because it
reduces the total spill pressure, and makes better use of it's (large)
instruction set.  Though the X86 backend doesn't know how to rewrite many
instructions yet, this already makes a substantial difference on 176.gcc for
example:

Before:
Time:
   8.0099 ( 31.2%)   0.0100 ( 12.5%)   8.0199 ( 31.2%)   7.7186 ( 30.0%)  Local Register Allocator

Code quality:
734559 asm-printer           - Number of machine instrs printed
111395 ra-local              - Number of registers reloaded
 79902 ra-local              - Number of registers spilled
231554 x86-peephole          - Number of peephole optimization performed

After:
Time:
   7.8700 ( 30.6%)   0.0099 ( 19.9%)   7.8800 ( 30.6%)   7.7892 ( 30.2%)  Local Register Allocator
Code quality:
733083 asm-printer           - Number of machine instrs printed
  2379 ra-local              - Number of reloads fused into instructions
109046 ra-local              - Number of registers reloaded
 79881 ra-local              - Number of registers spilled
230658 x86-peephole          - Number of peephole optimization performed

So by fusing 2300 instructions, we reduced the  static number of instructions
by 1500, and reduces the number of peepholes (and thus the work) by about 900.
This also clearly reduces the number of reload/spill instructions that are
emitted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11542 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 08:09:40 +00:00
Chris Lattner
cdee28724e Fix a bug in my previous refactoring change... arg!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11535 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 07:02:17 +00:00
Chris Lattner
1e3812c1c5 Once we have a way to fold spill code reloads into instructions, we have a way to use it. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11517 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 04:08:37 +00:00
Chris Lattner
42e0a8fded Refactor code a bit. No functionality changes, though the comment hints at things to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11515 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 03:57:19 +00:00
Alkis Evlogimenos
859a18b583 Make dense maps keyed on physical registers smallerusing
MRegisterInfo::getNumRegs() instead of
MRegisterInfo::FirstVirtualRegister.

Also use MRegisterInfo::is{Physical,Virtual}Register where
appropriate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11477 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-15 21:37:17 +00:00
Alkis Evlogimenos
be766c7246 Remove getAllocatedRegNum(). Use getReg() instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11393 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-13 21:01:20 +00:00
Alkis Evlogimenos
4de473bc59 Use getNumVirtualRegs().
Whitespace cleanups.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11389 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-13 18:20:47 +00:00
Alkis Evlogimenos
c0b9dc5be7 Change MachineBasicBlock's vector of MachineInstr pointers into an
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-12 02:27:10 +00:00
Chris Lattner
1cbe4d0ad0 Do not use MachineOperand::isVirtualRegister either!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11283 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-10 21:12:22 +00:00
Chris Lattner
3d878d80d6 Eliminate users of MachineOperand::isPhysicalRegister
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11278 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-10 20:41:10 +00:00
Chris Lattner
ecea5635f8 Another nice speedup for the register allocator. This time, we replace
the Virt2PhysRegMap std::map with an std::vector.  This speeds up the
register allocator another (almost) 40%, from .72->.45s in a release build
of LLC on 253.perlbmk.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11219 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-09 02:12:04 +00:00
Chris Lattner
64667b6418 Change the PhysRegsUsed map into a dense array. Seeing that this is a mapping
from physical registers, and they are always dense, it makes sense to not have
a ton of RBtree overhead.  This change speeds up regalloclocal about ~30% on
253.perlbmk, from .35s -> .27s in the JIT (in LLC, it goes from .74 -> .55).

Now live variable analysis is the slowest codegen pass.  Of course it doesn't
help that we have to run it twice, because regalloclocal doesn't update it,
but even if it did it would be the slowest pass (now it's just the 2x slowest
pass :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11215 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-09 01:26:13 +00:00
Chris Lattner
ef09c63e7b Finegrainify namespacification, use new MRegisterInfo::isVirtualRegister
method


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11037 91177308-0d34-0410-b5e6-96231b3b80d8
2004-01-31 21:27:19 +00:00
Alkis Evlogimenos
19b6486d38 Correctly compute live variable information for physical registers
when an implicitely defined register is later used by an alias. For example:

         call foo
         %reg1024 = mov %AL

The call implicitely defines EAX but only AL is used. Before this fix
no information was available on AL. Now EAX and all its aliases except
AL get defined and die at the call instruction whereas AL lives to be
killed by the assignment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10813 91177308-0d34-0410-b5e6-96231b3b80d8
2004-01-13 06:24:30 +00:00
Alkis Evlogimenos
4c080863de Remove TwoAddressInstruction from the public headers and add an ID
instead, since this pass doesn't expose any state to its users.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10520 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-18 22:40:24 +00:00
Alkis Evlogimenos
9af9dbde7d Modify local register allocator to use the two-address instruction pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10513 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-18 13:08:52 +00:00
Alkis Evlogimenos
4d7af65903 Change interface of MachineOperand as follows:
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10461 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-14 13:24:17 +00:00
Alkis Evlogimenos
efe995a406 Remove unecessary if statements when looping on ImplicitDefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10444 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-13 01:20:58 +00:00
Alkis Evlogimenos
a327e7fea9 Make assertion stricter. Since the source operands are allocated at
this point, the second operand must be a physical register (it cannot
be a virtual one).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10292 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-05 11:31:39 +00:00
Brian Gaeke
d0fde30ce8 Put all LLVM code into the llvm namespace, as per bug 109.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-11 22:41:34 +00:00
Chris Lattner
3e43026095 standardize command line option names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9496 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-24 20:05:58 +00:00
John Criswell
b576c94c15 Added LLVM project notice to the top of every C++ source file.
Header files will be on the way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9298 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-20 19:43:21 +00:00
Alkis Evlogimenos
73ff5120eb Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs
and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:

if (const unsigned* AS = TID.ImplicitDefs) {
  for (int i = 0; AS[i]; ++i) {
    // use AS[i]
  }
}

was changed to:

for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
  // use *AS
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8960 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-08 05:20:08 +00:00
Chris Lattner
41822c790f Fix bug: Jello/2003-08-23-RegisterAllocatePhysReg.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8095 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-23 23:49:42 +00:00
Chris Lattner
128c2aa493 Fix bug: Jello/2003-08-15-AllocaAssertion.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7916 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-17 18:01:15 +00:00
Brian Gaeke
53b99a0fe7 Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7906 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-15 21:19:25 +00:00
Brian Gaeke
19df3876e6 Factory methods for FunctionPasses now return type FunctionPass *.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7823 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-13 18:18:15 +00:00
Chris Lattner
8c8194500d Fix bugs handling ESP in alloca references
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7591 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-05 04:13:58 +00:00
Chris Lattner
d9ac6a7d3b Revert previous change, and be really anal about what physical registers can do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7588 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-05 00:49:09 +00:00
Chris Lattner
27615d7f21 Don't bother calculating info unless its needed. May reduce number of stack slots created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7584 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-04 23:42:37 +00:00
Chris Lattner
b8822ad224 * Fix spelling of 'necessary'
* Add a lot more DEBUG output, which is better structured than before
* Fix bug: Jello/2003-08-04-PhysRegLiveFailure.llx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7583 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-04 23:36:39 +00:00
Chris Lattner
4cc662b0ef Set debug types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7533 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:47:31 +00:00
Chris Lattner
d3fd79f699 Wrap at 80 columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7503 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 13:49:03 +00:00
Chris Lattner
a11136b16c Move DEBUG to Debug.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7497 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-01 22:21:34 +00:00
Vikram S. Adve
5f2180c533 (1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 00:05:23 +00:00
Chris Lattner
d5725631c5 Fix tab infestation!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6109 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-12 03:54:14 +00:00
Misha Brukman
15b55e20cc Debug output should go to cerr, not cout, because that's where bytecode goes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6002 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-04 22:51:30 +00:00
Chris Lattner
0416d2a70a Fix problems with empty basic blocks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5326 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-16 18:06:43 +00:00
Chris Lattner
3501feab81 Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-14 22:00:31 +00:00