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7b73a5d6de
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566 Commits

Author SHA1 Message Date
Rafael Espindola
7b73a5d6de split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43176 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-19 14:35:17 +00:00
Chris Lattner
3a7c33a853 Add an easy microoptimization I noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43164 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-19 03:29:26 +00:00
Evan Cheng
f0a0cddbcd - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. 
- Fix some copy+paste bugs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-18 22:40:57 +00:00
Evan Cheng
58184e6878 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-18 21:29:24 +00:00
Christopher Lamb
a4c791072f Fix a misnamed parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43145 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-18 19:29:45 +00:00
Chris Lattner
65a3323b0a legalizing the ret operation on f64 shouldn't introduce a new 
i64 bit convert needlessly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43116 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-18 06:17:07 +00:00
Evan Cheng
347d39f1fd Revert 42908 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42960 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-14 05:57:21 +00:00
Dan Gohman
8ddde0a151 Change the names used for internal labels to use the current 
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42908 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 14:53:36 +00:00
Dan Gohman
f96e4de403 Set ISD::FPOW to Expand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42881 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-11 23:21:31 +00:00
Dan Gohman
525178cdbf Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to 
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-08 18:33:35 +00:00
Evan Cheng
66f0f64082 - Added a few target hooks to generate load / store instructions from / to any 
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-05 01:32:41 +00:00
Dan Gohman
cb406c2597 Use empty() member functions when that's what's being tested for instead 
of comparing begin() and end().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42585 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-03 19:26:29 +00:00
Gordon Henriksen
cd8bc05102 AsmPrinters overriding getAnalysisUsage should call super. 
And not super's super, either.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42482 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-30 13:39:29 +00:00
Evan Cheng
9efce638d3 Allow copyRegToReg to emit cross register classes copies. 
Tested with "make check"!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-26 06:25:56 +00:00
Dan Gohman
677ccc6e8b More explicit keywords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42316 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-25 20:27:06 +00:00
Evan Cheng
76a4023096 Honor user-defined section specification of a global, ignores whether its initializer is null. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42182 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-21 00:41:19 +00:00
Evan Cheng
17207ddf38 Enable if-conversion for ARM by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42156 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-20 00:48:22 +00:00
Evan Cheng
e71bff7405 Avoid referencing deleted instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42153 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-19 21:48:07 +00:00
Dan Gohman
92dfe2001e Remove isReg, isImm, and isMBB, and change all their users to use 
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-14 20:33:02 +00:00
Bill Wendling
fe4afb17d3 Enable indirect encoding for the personality function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41873 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 23:55:40 +00:00
Evan Cheng
071a279e94 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 19:55:27 +00:00
Duncan Sands
f7331b3dd7 Fold the adjust_trampoline intrinsic into 
init_trampoline.  There is now only one
trampoline intrinsic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 14:10:23 +00:00
Evan Cheng
be36798bfe 80 col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41812 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-10 22:22:23 +00:00
Chris Lattner
bf8ae84a21 Add some notes about better flag handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41808 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-10 21:43:18 +00:00
Owen Anderson
718cb665ca Add lengthof and endof templates that hide a lot of sizeof computations. 
Patch by Sterling Stein!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-07 04:06:50 +00:00
Dale Johannesen
eaf089430e Enhance APFloat to retain bits of NaNs (fixes oggenc). 
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-31 04:03:46 +00:00
Raul Herbster
8c132633c8 Instruction formats added used to generate multiply instructions of V5TE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41629 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:34:14 +00:00
Raul Herbster
b94e60872e Unused relocation type reloc_arm_absolute removed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41628 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:31:35 +00:00
Raul Herbster
9c1a3827ce Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41627 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:29:26 +00:00
Raul Herbster
37fb5b154c ARM instruction table was modified by adding information to generate multiply instruction of V5TE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41626 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:25:47 +00:00
Raul Herbster
d05c04c169 JITInfo now resolves function addrs and also relocations. It always emits a stub. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41625 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:21:27 +00:00
Evan Cheng
35b35c5c32 Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 05:52:20 +00:00
Evan Cheng
0ff94f7fcc Initial JIT support for ARM by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 01:37:15 +00:00
Dan Gohman
61e729e2e9 More explicit keywords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 21:21:54 +00:00
Evan Cheng
7fc77611ef Indexed loads each has 2 outputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40658 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 00:12:08 +00:00
Dan Gohman
f452207d20 More explicit keywords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40589 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-30 14:51:59 +00:00
Duncan Sands
36397f5034 Support for trampolines, except for X86 codegen which is 
still under discussion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-27 12:58:54 +00:00
Dan Gohman
b8275a3f6f Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-25 19:33:14 +00:00
Evan Cheng
ffbaccae02 No more noResults. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-21 00:34:19 +00:00
Evan Cheng
8bd6035750 Added -print-emitted-asm to print out JIT generated asm to cerr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-20 21:56:13 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Evan Cheng
4558b807a2 Only adjust esp around calls in presence of alloca. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40030 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 00:42:58 +00:00
Chris Lattner
c3dbe70ce7 no email addrs in file headers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39962 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 05:56:43 +00:00
Anton Korobeynikov
2365f51ed0 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-14 14:06:15 +00:00
Dale Johannesen
66a2a8f878 ARM: make branch folder remove unconditional branches 
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39782 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-12 16:45:35 +00:00
Dale Johannesen
5d9c4b6020 Fix hang compiling TimberWolf (allow for islands 
of size other than 4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39743 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 18:32:38 +00:00
Evan Cheng
8202010364 Didn't mean the last commit. Revert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38515 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 22:00:16 +00:00
Evan Cheng
c608ff22e7 Update. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38513 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 21:49:47 +00:00
Evan Cheng
13ab020ea0 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:08:01 +00:00
Chris Lattner
87bdba6d6a The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38463 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-09 17:25:29 +00:00