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Commit Graph

4894 Commits

Author SHA1 Message Date
Andrew Trick
4bbf4678e3 Improve pre-RA-sched register pressure tracking for duplicate operands.
This helps cases like 2008-07-19-movups-spills.ll, but doesn't have an obvious impact on benchmarks


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 19:12:43 +00:00
Benjamin Kramer
d7cdc3e1f9 Fix typo, make helper static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127335 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 16:19:12 +00:00
Eric Christopher
29449448b0 Fix some latent bugs if the nodes are unschedulable. We'd gotten away
with this before since none of the register tracking or nightly tests
had unschedulable nodes.

This should probably be refixed with a special default Node that just
returns some "don't touch me" values.

Fixes PR9427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127263 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08 19:35:47 +00:00
Andrew Trick
0bf56c821c Further improvements to pre-RA-sched=list-ilp.
This change uses the MaxReorderWindow for both height and depth, which
tends to limit the negative effects of high register pressure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08 01:51:56 +00:00
Cameron Zwarich
be2119e8e2 Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07 21:56:36 +00:00
Owen Anderson
6154f6c929 Use the correct LHS type when determining the legalization of a shift's RHS type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07 18:29:47 +00:00
Eric Christopher
b43034d700 Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-06 21:13:45 +00:00
Andrew Trick
3c6e49504e Disable a couple of experimental heuristics to get the best results from the current implementation of -pre-RA-sched=list-ilp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-06 00:03:32 +00:00
Andrew Trick
afc7d235e9 Be explicit with abs(). Visual Studio workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127075 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 10:29:25 +00:00
Andrew Trick
5e84e3ccaa Fix for -sched-high-latency-cycles in sched=list-ilp mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 09:18:16 +00:00
Andrew Trick
ab2e3e2d70 Missing comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 08:04:11 +00:00
Andrew Trick
e0ef509aeb Increased the register pressure limit on x86_64 from 8 to 12
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.

Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.

Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 08:00:22 +00:00
Duncan Sands
53dfa78e41 Revert commit 126684 "Use the correct shift amount type". It is only the correct
type after type legalization has completed.  Before then it may simply not be big
enough to hold the shift amount, particularly on x86 which uses a very small type
for shifts (this issue broke stuff in the past which is why LegalizeTypes carefully
uses a large type for shift amounts).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 14:28:59 +00:00
Andrew Trick
a0807f57ca Minor pre-RA-sched fixes and cleanup.
Fix the PendingQueue, then disable it because it's not required for
the current schedulers' heuristics.
Fix the logic for the unused list-ilp scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 02:03:45 +00:00
Bill Wendling
e7147dba73 There are times when the landing pad won't have a call to 'eh.selector' in
it. It's been assumed up til now that it would be in its immediate
successor. However, this isn't necessarily the case. It could be in one of its
successor's successors.

Modify the code to more thoroughly check for an 'eh.selector' call in
successors. It only looks at a successor if we get there as a result of an
unconditional branch.

Testcase ObjC/exceptions-4.m in r126968.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 23:14:05 +00:00
Eli Friedman
81c5ef8649 Revert r123908; the code in question is completely untested and wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 22:33:23 +00:00
Bob Wilson
254c63e336 Avoid exponential blow-up when printing DAGs.
David Greene changed CannotYetSelect() to print the full DAG including multiple
copies of operands reached through different paths in the DAG.  Unfortunately
this blows up exponentially in some cases.  The depth limit of 100 is way too
high to prevent this -- I'm seeing a message string of 150MB with a depth of
only 40 in one particularly bad case, even though the DAG has less than 200
nodes.  Part of the problem is that the printing code is following chain
operands, so if you fail to select an operation with a chain, the printer will
follow all the chained operations back to the entry node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126899 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 23:38:06 +00:00
Stuart Hastings
7e33418671 Can't introduce floating-point immediate constants after legalization.
Radar 9056407.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 19:36:30 +00:00
Duncan Sands
e80338af3f Add a few missed unary cases when legalizing vector results. Put some cases
in alphabetical order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126745 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 15:15:43 +00:00
Jim Grosbach
9d40193d79 trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 01:39:05 +00:00
Jim Grosbach
2d76c84514 Generalize the register matching code in DAGISel a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 01:37:19 +00:00
Owen Anderson
6973289208 Use the correct shift amount type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126684 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 21:10:10 +00:00
Owen Anderson
c6d160bfa2 Clean whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126683 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 20:57:56 +00:00
Duncan Sands
9c45251e11 Legalize support for fpextend of vector. PR9309.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126574 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27 14:41:27 +00:00
Nadav Rotem
fcd96199f5 Fix typos in the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27 07:40:43 +00:00
Tobias Grosser
a91f86c49a Pass the graph to the DOTGraphTraits.getEdgeAttributes().
This follows the interface of getNodeAttributes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27 04:11:03 +00:00
Benjamin Kramer
7466678003 Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic.
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-26 22:48:07 +00:00
Owen Anderson
95771afbfd Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25 21:41:48 +00:00
Jim Grosbach
3fc8317798 Fix formatting of debug helper string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25 03:59:03 +00:00
Cameron Zwarich
8fbbdca45c Set NumSignBits to 1 if KnownZero/KnownOne are being zero extended. In theory it
is possible to do better if the high bit is set in either KnownZero/KnownOne, but
in practice NumSignBits is always 1 when we are zero extending because nothing
is known about that register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126465 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25 01:11:01 +00:00
Cameron Zwarich
33b554795d We only want to zero extend the existing information if the bit width is
actually larger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126464 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25 01:10:55 +00:00
Nadav Rotem
8c20ec54d9 Enable support for vector sext and trunc:
Limit the folding of any_ext and sext  into the load operation to scalars.
Limit the active-bits trunc optimization to scalars.
Document vector trunc and vector sext in LangRef.

Similar to commit 126080 (for enabling zext).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 21:01:34 +00:00
Cameron Zwarich
8ca814c4e0 Merge information about the number of zero, one, and sign bits of live-out
registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:25 +00:00
Cameron Zwarich
9b6af8de58 Add a getNumSignBits() method to APInt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126379 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:20 +00:00
Cameron Zwarich
324a24f6aa Add a mechanism for invalidating the LiveOutInfo of a PHI, and use it whenever
a block is visited before all of its predecessors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:16 +00:00
Cameron Zwarich
a46cd97818 Track blocks visited in reverse postorder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:13 +00:00
Cameron Zwarich
e1497b9791 Refactor the LiveOutInfo interface into a few methods on FunctionLoweringInfo
and make the actual map private.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:08 +00:00
Cameron Zwarich
2dbe2850d0 Have isel visit blocks in reverse postorder rather than an undefined order. This
allows for the information propagated across basic blocks to be merged at phis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:04 +00:00
Cameron Zwarich
4ecc82e592 Roll out r126169 and r126170 in an attempt to fix the selfhost bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 03:24:52 +00:00
Cameron Zwarich
92efda7e91 Merge information about the number of zero, one, and sign bits of live-out registers
at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine
phase. This fixes <rdar://problem/8760114>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 00:46:27 +00:00
Cameron Zwarich
63a8dae64d Have isel visit blocks in reverse postorder rather than an undefined order. This
allows for the information propagated across basic blocks to be merged at phis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126169 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 00:46:22 +00:00
Devang Patel
68e6beeccc Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location.  The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working. 
 - The debugger needs to be aware of prolog_end attribute attached with line table entries.
 - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-21 23:21:26 +00:00
Nadav Rotem
ed9b934f65 Fix 9267; Add vector zext support.
The DAGCombiner folds the zext into complex load instructions. This patch
prevents this optimization on vectors since none of the supported targets
knows how to perform load+vector_zext in one instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-20 12:37:50 +00:00
Devang Patel
a778f5c798 Do not lose debug info of an inlined function argument even if the argument is only used through GEPs.
This time with a fix that avoids using invalidated DenseMap iterator.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125984 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18 22:43:42 +00:00
Cameron Zwarich
1646953538 Roll out r125794 to help diagnose the llvm-gcc-i386-linux-selfhost failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18 04:58:10 +00:00
Devang Patel
a4defc00eb Do not lose debug info of an inlined function argument even if the argument is only used through GEPs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-17 23:33:27 +00:00
Duncan Sands
fbd53f79f5 Fix wrong logic in promotion of signed mul-with-overflow (I pointed this out at
the time but presumably my email got lost).  Examples where the previous logic
got it wrong: (1) a signed i8 multiply of 64 by 2 overflows, but the high part is
zero; (2) a signed i8 multiple of -128 by 2 overflows, but the high part is all
ones. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-17 12:42:48 +00:00
Stuart Hastings
a901129169 Swap VT and DebugLoc operands of getExtLoad() for consistency with
other getNode() methods.  Radar 9002173.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16 16:23:55 +00:00
Eric Christopher
7bccf6abdc Refactor zero folding slightly. Clean up todo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16 04:50:12 +00:00
Eric Christopher
169e1552e7 The change for PR9190 wasn't quite right. We need to avoid making the
transformation if we can't legally create a build vector of the correct
type. Check that we can make the transformation first, and add a TODO to
refactor this code with similar cases.

Fixes: PR9223 and rdar://9000350


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16 01:10:03 +00:00