Johnny Chen
c6f7b27fda
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-11 18:12:29 +00:00
Jim Grosbach
4152778605
Radar 7417921
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tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95686 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09 19:51:37 +00:00
Jim Grosbach
a87ded2695
tighten up eh.setjmp sequence a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-08 23:22:00 +00:00
Jim Grosbach
c90a153ad0
Adjust setjmp instruction sequence to not need 32-bit alignment padding
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94627 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-27 00:07:20 +00:00
Jim Grosbach
d5d2baec26
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
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cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-22 00:08:13 +00:00
Johnny Chen
eb231ce51d
The most significant encoding bit of GPR:$src or GPR:$dst was over-specified in
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the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch). Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93759 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-18 20:15:56 +00:00
Johnny Chen
51bc5612b3
Added 16-bit Thumb Load/Store immediate instructions with encoding bits so that
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the disassembler can properly decode Load/Store register/immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-14 22:42:17 +00:00
Johnny Chen
12360917ef
Fixed a couple of places for Thumb MOV where encoding bits are underspecified.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-13 21:00:26 +00:00
Jakob Stoklund Olesen
c5b7ef1519
Remove the JustSP single-register regclass.
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It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-13 00:43:06 +00:00
Jakob Stoklund Olesen
24b34f8f3e
Add a SPR register class to the ARM target.
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Certain Thumb instructions require only SP (e.g. tSTRspi).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91944 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 23:54:44 +00:00
Johnny Chen
caedfbc6ae
Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91571 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 23:36:52 +00:00
Johnny Chen
bbc71b2904
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
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bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91496 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 02:32:54 +00:00
Johnny Chen
d68e119c0f
Added encoding bits for the Thumb ISA. Initial checkin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91434 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 17:24:14 +00:00
Jim Grosbach
d122874996
Thumb1 exception handling setjmp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90246 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01 18:10:36 +00:00
Evan Cheng
4aedb61d03
Remat VLDRD from constpool. Clean up some instruction property specifications.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 19:57:15 +00:00
Evan Cheng
2ef9c8a43d
More consistent thumb1 asm printing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-19 06:57:41 +00:00
Evan Cheng
b9803a8fa6
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
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load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 23:52:48 +00:00
Evan Cheng
b9f51cbe98
The .n suffix must go after the predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86019 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-04 07:38:48 +00:00
Evan Cheng
7883fa942f
Use ldr.n to workaround a darwin assembler bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85980 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-04 00:00:39 +00:00
Bob Wilson
af14e663ac
For Thumb indirect branches, use "mov pc, reg" which does not switch
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between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85874 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 06:29:56 +00:00
Bob Wilson
907eebd5a6
Put BlockAddresses into ARM constant pools.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 20:59:23 +00:00
Evan Cheng
de17fb6e4d
Use cbz and cbnz instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85698 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 23:46:45 +00:00
Bob Wilson
ddb16df912
Add ARM codegen for indirect branches.
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clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30 05:45:42 +00:00
Dan Gohman
533297b58d
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29 18:10:34 +00:00
Bob Wilson
8d4de5abfa
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
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opcode and operand with a tab. Check for these instructions in the usual
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28 18:26:41 +00:00
Evan Cheng
699bebac4f
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 00:08:59 +00:00
Evan Cheng
0d92f5f768
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
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ld / st pairs, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 08:22:27 +00:00
Evan Cheng
d20d658675
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 01:33:39 +00:00
Jim Grosbach
c732adf3a1
Add "isBarrier = 1" to return instructions.
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Patch by Sylvere Teissier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83135 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 01:35:11 +00:00
Evan Cheng
cdf23b950a
Remove comments which don't add much to .s readibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81306 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 01:38:23 +00:00
David Goodwin
e8d82c0e4f
Calls clobber FPSCR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80956 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-03 22:12:28 +00:00
Evan Cheng
029599bf01
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80615 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-31 20:14:07 +00:00
Evan Cheng
d17479e845
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80350 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-28 06:59:37 +00:00
Evan Cheng
0e87e23f6e
v4, v5 does not support sxtb / sxth.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80322 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-28 00:31:43 +00:00
Bob Wilson
4f38b383d5
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
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several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-21 21:58:55 +00:00
Evan Cheng
89d177f017
Fix an obvious copy-n-paste bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79535 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-20 17:01:04 +00:00
David Goodwin
5d598aaf3d
Update Cortex-A8 instruction itineraries for integer instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19 18:00:44 +00:00
Evan Cheng
51f39961c3
Fix revsh pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79318 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18 05:43:23 +00:00
Evan Cheng
31b99dd760
Also shrink immediate branches; also more assembler workarounds.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79014 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 18:31:44 +00:00
Evan Cheng
a1efbbdbf3
Shrink ADR and LDR from constantpool late during constantpool island pass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78970 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 00:32:16 +00:00
David Goodwin
6d3d9c3fc3
Finalize itineraries for cortex-a8 integer multiply
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13 15:51:13 +00:00
David Goodwin
1a8f36e3ce
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 18:31:53 +00:00
Evan Cheng
007ea274f4
Shrink Thumb2 movcc instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78790 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 05:17:19 +00:00
Evan Cheng
c972165b11
80 col violation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78778 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 02:03:03 +00:00
Evan Cheng
b89030ab65
Shrinkify Thumb2 r = add sp, imm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78745 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 23:00:31 +00:00
Evan Cheng
4b322e58b7
Shrinkify Thumb2 load / store multiple instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 21:11:32 +00:00
Owen Anderson
825b72b057
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
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the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 20:47:22 +00:00
Owen Anderson
e50ed30282
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:56:29 +00:00
Evan Cheng
e8af1f9afe
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 02:37:24 +00:00
Anton Korobeynikov
8e9ece75db
Use subclassing to print lane-like immediates (w/o hash) eliminating
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'no_hash' modifier. Hopefully this will make Daniel happy :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 23:10:41 +00:00