6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-12 03:32:10 +00:00
Code Issues Projects Releases Wiki Activity
69,536 Commits 39 Branches 0 Tags
Commit Graph

4807 Commits

Author SHA1 Message Date
Eric Christopher
76dda7ec1d Recommit this change and remove the failing part of the test - it didn't 
pass in the first place and was masked by earlier failures not warning
and aborting the block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119184 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 21:11:06 +00:00
Jakob Stoklund Olesen
a284aa1657 Fix PR8612 in the standard spiller as well. 
The live range of a register defined by an early clobber starts at the use slot,
not the def slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 20:55:53 +00:00
Jakob Stoklund Olesen
68257e61eb When spilling a register defined by an early clobber, make sure that the new 
live ranges for the spill register are also defined at the use slot instead of
the normal def slot.

This fixes PR8612 for the inline spiller. A use was being allocated to the same
register as a spilled early clobber def.

This problem exists in all the spillers. A fix for the standard spiller is
forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 20:55:49 +00:00
Chris Lattner
513dbf1af0 remove a pointless testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 05:07:03 +00:00
Chris Lattner
dd57417c08 remove some extraneous quotes to make the new instprinter match. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119104 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 02:43:46 +00:00
Chris Lattner
261bc89fa1 add some nounwind's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119086 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-14 22:22:14 +00:00
Peter Collingbourne
948cf0289f Recognise 32-bit ror-based bswap implementation used by uclibc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119007 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 19:54:30 +00:00
Evan Cheng
63f3544a7f Add conditional move of large immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 02:25:14 +00:00
Evan Cheng
e5e0ef180e Fix an obvious typo which inverted an immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 00:27:47 +00:00
Eric Christopher
6eb39a09b4 This should be still failing, but is. Disable it with the 
forget-me-stick for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 00:25:06 +00:00
Evan Cheng
875a6ac09a Add conditional mvn instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 22:42:47 +00:00
Evan Cheng
529916ca4a Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118922 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 20:32:20 +00:00
Andrew Trick
11f20edcf9 Emacs auto-fill bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118908 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 18:17:46 +00:00
Andrew Trick
4252ffdef6 Test case for PR8287: SD scheduling time. Fixed in r118904. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118906 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 17:57:22 +00:00
Kalle Raiskila
7ea1ab5f41 Fix memory access lowering on SPU, adding 
support for the case where alignment<value size.

These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory 
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 10:14:03 +00:00
Bruno Cardoso Lopes
7d5652dcd5 Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118864 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 00:38:32 +00:00
Dan Gohman
efb8a9d0c2 Remove the memmove->memcpy optimization from CodeGen. MemCpyOpt does this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 16:24:49 +00:00
Bruno Cardoso Lopes
0cf2b2b9f0 Add a test to the previous added clo instruction. Patch by Akira again 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118668 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 02:22:44 +00:00
Bob Wilson
54f9256380 Do not use MEMBARRIER_MCR for any Thumb code. 
It is only supported for ARM code.  Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled.  This prevents a "cannot select MEMBARRIER_MCR" error in that
situation.  Radar 8644195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 22:50:44 +00:00
Duncan Sands
68c39552a5 Testcase for PR8211 (llc crash at -O0). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 16:22:27 +00:00
Dan Gohman
6a559cd695 Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shl 
in order to fold it into a load.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118471 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 01:54:35 +00:00
Dan Gohman
be7c5116a7 Delete an extraneous svn:executable property. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118470 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 01:51:06 +00:00
Dale Johannesen
71365d3774 Fix an inline asm pasto from 117667; was preventing 
{i64, i64} from matching i128.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118465 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 01:15:07 +00:00
Owen Anderson
c24cb3551e Add support for ARM's specialized vector-compare-against-zero instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 23:21:22 +00:00
Dale Johannesen
7179d1e5c0 Revert 118422 in search of bot verdancy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 19:17:22 +00:00
Jason W Kim
69ad7138b7 Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 17:58:07 +00:00
Chris Lattner
db28788e4a go to great lengths to work around a GAS bug my previous patch 
exposed:

GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.

Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).

As such, switch the canonical form of this instruction to "pi" instead
of "ip".  This makes the code generator and disassembler generate pi,
avoiding the gas bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-06 21:37:06 +00:00
Owen Anderson
080c092297 Add codegen and encoding support for the immediate form of vbic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-05 19:27:46 +00:00
Duncan Sands
1e92ec6886 When passing a huge parameter using the byval mechanism, a long 
sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead.  PR7170.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118260 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 21:16:46 +00:00
Evan Cheng
416941d50f Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 05:19:35 +00:00
Owen Anderson
60f4870c22 Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. 
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 23:15:26 +00:00
Owen Anderson
d966817f3c Add support for code generation of the one register with immediate form of vorr. 
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 22:44:51 +00:00
Evan Cheng
949c910fb3 Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 18:21:33 +00:00
Dale Johannesen
d5ce456161 This test assumes SSE is present; that is not the default 
on non-X86 hosts.  Hopefully fixes ppc-host buildbot.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 18:08:41 +00:00
Bob Wilson
d168cef664 Add codegen patterns for VST1-lane instructions. Radar 8599955. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 16:24:53 +00:00
Bob Wilson
3468c2ee20 Check for extractelement with a variable operand for the element number. 
For NEON we had been assuming this was always an immediate constant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 16:24:50 +00:00
Evan Cheng
dfed19fe2c Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 06:34:55 +00:00
Evan Cheng
bc7deb0f75 Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 05:14:24 +00:00
Dan Gohman
394d6298bc Fix DAGCombiner to avoid going into an infinite loop when it 
encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118143 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:47:46 +00:00
Evan Cheng
8239daf7c8 Two sets of changes. Sorry they are intermingled. 
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 00:45:17 +00:00
John Thompson
45c21ff044 Inline asm mult-alt constraint tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118107 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 23:01:44 +00:00
Jim Grosbach
ab3d00e535 Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke 
assumptions about stack layout. Specifically, LR must be saved next to FP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 17:35:25 +00:00
Devang Patel
a90b305af9 Use frameindex, if available, as a last resort to emit debug info for a parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 17:01:30 +00:00
Bob Wilson
665814b6be Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 23:40:51 +00:00
Bob Wilson
baf0615426 Add VLD1-lane testcases for quad-register types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117975 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 23:40:46 +00:00
Bob Wilson
b796bbb6de Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 22:04:05 +00:00
Bill Wendling
40a5eb18b0 When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 20:41:43 +00:00
Bob Wilson
24645a1a6d NEON does not support truncating vector stores. Radar 8598391. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 18:31:39 +00:00
Bill Wendling
504fb4fb8e More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the 
peephole optimizer is disabled. That's not good at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117905 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 05:59:43 +00:00
Bill Wendling
59707e8055 Disable because peephole is disabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117903 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 05:48:44 +00:00