Evan Cheng
600c043697
- Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots.
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- Mark MOVUPSrm re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88974 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 21:56:03 +00:00
Jim Grosbach
2f74603460
Convert to FileCheck
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88947 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 20:04:15 +00:00
Lang Hames
0d6dd493f4
Added a testcase for PR5495.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88946 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 20:03:13 +00:00
Jim Grosbach
4adcade9b7
Convert to FileCheck
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88942 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 19:46:46 +00:00
Jim Grosbach
c0517504e5
tbb opt off by default
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88921 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 17:24:45 +00:00
David Greene
ddff941357
Support spill comments.
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Have the asm printer emit a comment if an instruction is a spill or
reload and have the spiller mark copies it introdues so the asm printer
can also annotate those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 15:12:23 +00:00
Evan Cheng
39aa7251a2
Check if subreg index is zero.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88899 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 06:31:49 +00:00
Evan Cheng
285a7d57dc
For some targets, a copy can use a register multiple times, e.g. ppc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88895 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 05:52:06 +00:00
Evan Cheng
2d947263d5
xfail for now. It has been failing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88892 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 05:44:04 +00:00
Bruno Cardoso Lopes
6e0b658dad
- Fix a small bug while handling target constant pools (one param was missing).
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- Add a smarter constant pool loading, instead of:
lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)
Generate:
lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88886 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 04:33:42 +00:00
Jim Grosbach
a44321776e
Detect need for autoalignment of the stack earlier to catch spills more
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conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-15 21:45:34 +00:00
Jim Grosbach
e11d26b3d8
remove xfail
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88817 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 21:57:35 +00:00
Richard Osborne
13c4fabf99
Add XCore support for arbitrary-sized aggregate returns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88802 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 19:33:35 +00:00
Evan Cheng
fae3e92345
Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88753 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 03:42:17 +00:00
Evan Cheng
d57cdd5683
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
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- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 02:55:43 +00:00
Evan Cheng
e17ae4f82e
Add radar number.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88739 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 02:11:32 +00:00
Evan Cheng
8fdd84cfa7
Fix PR5412: Fix an inverted check and another missing sub-register check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88738 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 02:09:09 +00:00
Dan Gohman
ed9bab3b4d
Enable the tail call optimization when the caller returns undef.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88737 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 02:06:30 +00:00
Evan Cheng
0cd22dd738
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 01:50:00 +00:00
Evan Cheng
1f6a3c820a
Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88719 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 23:16:41 +00:00
Dan Gohman
c4c550c758
When optimizing for size, don't tail-merge unless it's likely to be a
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code-size win, and not when it's only likely to be code-size neutral,
such as when only a single instruction would be eliminated and a new
branch would be required.
This fixes rdar://7392894.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88692 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 21:02:15 +00:00
Evan Cheng
236490d870
Fix PR5410: LiveVariables lost subreg def:
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D0<def,dead> = ...
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= S0<use, kill>
S0<def> = ...
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D0<def> =
The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88690 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 20:36:40 +00:00
Dan Gohman
01205a80f5
Don't let a noalias difference disrupt the tailcall optimization.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88672 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 18:49:38 +00:00
Dale Johannesen
1e608819aa
Adjust isConstantSplat to allow for big-endian targets.
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PPC is such a target; make it work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87060 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 01:45:18 +00:00
Daniel Dunbar
6242495be2
Update test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87049 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 01:01:58 +00:00
Jim Grosbach
cb2c2b738a
Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86997 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 17:19:09 +00:00
Benjamin Kramer
9e3728be62
Fix typo in run line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86984 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 12:35:27 +00:00
Evan Cheng
60f9061820
RegScavenger::enterBasicBlock should always reset register state.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86972 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 07:49:10 +00:00
Evan Cheng
586f69a118
- Teach LSR to avoid changing cmp iv stride if it will create an immediate that
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cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86969 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 07:35:05 +00:00
Dan Gohman
ad6af45dc1
Tail merge at any size when there are two potentials blocks and one
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can be made to fall through into the other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86909 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 00:39:10 +00:00
Kenneth Uildriks
c158dde219
x86 users can now return arbitrary sized structs. Structs too large to fit in return registers will be returned through a hidden sret parameter introduced during SelectionDAG construction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86876 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 19:59:24 +00:00
Dan Gohman
2210c0bea8
Add support for tail duplication to BranchFolding, and extend
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tail merging support to handle more cases.
- Recognize several cases where tail merging is beneficial even when
the tail size is smaller than the generic threshold.
- Make use of MachineInstrDesc::isBarrier to help detect
non-fallthrough blocks.
- Check for and avoid disrupting fall-through edges in more cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86871 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 19:48:59 +00:00
Evan Cheng
012397489b
Add nounwind.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86814 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 07:11:02 +00:00
Bill Wendling
5606ec894e
Fix test to work on every platform.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86786 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 01:44:22 +00:00
Bill Wendling
13f6135742
Fix test to work on every platform.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86785 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 01:41:32 +00:00
Bill Wendling
ee161a6824
Make sure that the exception handling data has the same visibility as the
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function it's generated for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86779 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 01:24:59 +00:00
Bill Wendling
6b41aba7ce
Test this on Darwin only.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86752 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 23:18:33 +00:00
Dale Johannesen
9a645cd9d4
Emit correct code when making a ConstantPool entry for a vector
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constant whose component type is not a legal type for the target.
(If the target ConstantPool cannot handle this type either, it has
an opportunity to merge elements. In practice any target with
8-bit bytes must support i8 *as data*). 7320806 (partial).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86751 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 23:16:41 +00:00
Bill Wendling
b19a5e9be6
Modify how the prologue encoded the "move" information for the FDE. GCC
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generates a sequence similar to this:
__Z4funci:
LFB2:
mflr r0
LCFI0:
stmw r30,-8(r1)
LCFI1:
stw r0,8(r1)
LCFI2:
stwu r1,-80(r1)
LCFI3:
mr r30,r1
LCFI4:
where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other
things are. We generated something more like this:
Leh_func_begin1:
mflr r0
stw r31, 20(r1)
stw r0, 8(r1)
Llabel1:
stwu r1, -80(r1)
Llabel2:
mr r31, r1
Note that we are missing the "mr" instruction. This patch makes it more like the
GCC output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86729 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 22:14:04 +00:00
Mike Stump
75adb32c60
Add testcase for recent checkin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86620 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 23:10:49 +00:00
Jim Grosbach
3f51147d44
Update test
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86614 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 22:59:01 +00:00
Jim Grosbach
e5165490b7
Use Unified Assembly Syntax for the ARM backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 00:11:35 +00:00
Anton Korobeynikov
f0b47b7f6d
Add and-not (bic) patterns. Based heavily on patch by Brian Lucas!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86471 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-08 15:33:12 +00:00
Anton Korobeynikov
52f28e9b63
Fix invalid operand updates & implement post-inc memory operands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86466 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-08 14:27:38 +00:00
Anton Korobeynikov
c2fd919ea2
It is invalid to infer the value type from the result #0 of the node
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since the instruction might use the other result of different type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86462 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-08 12:14:54 +00:00
Nate Begeman
0b10b91465
x86 vector shuffle cleanup/fixes:
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1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect. The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86415 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 23:17:15 +00:00
Anton Korobeynikov
6534f83ae8
Add some dummy support for post-incremented loads
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86385 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 17:15:06 +00:00
Anton Korobeynikov
8983da729a
Add 8 bit libcalls and make use of them for msp430
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86384 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 17:14:39 +00:00
Anton Korobeynikov
123ed8f099
Initial support for addrmode handling. Tests by Brian Lucas!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86382 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 17:13:35 +00:00
Anton Korobeynikov
e8ea011cc7
It turns out that the testcase in question uncovered subreg-handling bug.
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Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86375 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 15:20:32 +00:00