Commit Graph

543 Commits

Author SHA1 Message Date
Daniel Sanders
02fbffd4e8 [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193695 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:45:42 +00:00
Daniel Sanders
c385709d83 [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics)
Also corrected the definition of the intrinsics for these instructions (the
result register is also the first operand), and added intrinsics for bsel and
bseli to clang (they already existed in the backend).

These four operations are mostly equivalent to bsel, and bseli (the difference
is which operand is tied to the result). As a result some of the tests changed
as described below.

bitwise.ll:
- bsel.v test adapted so that the mask is unknown at compile-time. This stops
  it emitting bmnzi.b instead of the intended bsel.v.
- The bseli.b test now tests the right thing. Namely the case when one of the
  values is an uimm8, rather than when the condition is a uimm8 (which is
  covered by bmnzi.b)

compare.ll:
- bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this
  is the same operation (see MSA.txt).

i8.ll
- CHECK-DAG-ized test.
- bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands
  because this is the same operation (see MSA.txt).
- bseli.b still emits bseli.b though because the immediate makes it
  distinguishable from bmnzi.b.

vec.ll:
- CHECK-DAG-ized test.
- bmz.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).
- bsel.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:20:38 +00:00
Daniel Sanders
6ff1ef9931 [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.

It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().

Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 14:45:14 +00:00
Daniel Sanders
a7c3cac871 [mips][msa] Combine binsri-like DAG of AND and OR into equivalent VSELECT
(or (and $a, $mask), (and $b, $inverse_mask)) => (vselect $mask, $a, $b).
where $mask is a constant splat. This allows bitwise operations to make use
of bsel.

It's also a stepping stone towards matching bins[lr], and bins[lr]i from
normal IR.

Two sets of similar tests have been added in this commit. The bsel_* functions
test the case where binsri cannot be used. The binsr_*_i functions will
start to use the binsri instruction in the next commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 13:51:01 +00:00
Daniel Sanders
57cd3bc406 [mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics)
splat.d is implemented but this subtest is currently disabled. This is because
it is difficult to match the appropriate IR on MIPS32. There is a patch under
review that should help with this so I hope to enable the subtest soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 13:07:44 +00:00
Akira Hatanaka
615a279f81 [mips] Align the stack to 16-bytes for mfp64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 19:29:03 +00:00
Reed Kotler
cb2280e4c7 Make first substantial checkin of my port of ARM constant islands code to Mips.
Before I just ported the shell of the pass. I've tried to keep everything
nearly identical to the ARM version. I think it will be very easy to eventually
merge these two and create a new more general pass that other targets can
use. I have some improvements I would like to make to allow pools to 
be shared across functions and some other things. When I'm all done we
can think about making a more general pass. More to be ported but the
basic mechanism works now almost as good as gcc mips16.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193509 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-27 21:57:36 +00:00
Daniel Sanders
09c7f4026a [mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193239 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-23 10:36:52 +00:00
Matheus Almeida
f89f66e61b [mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 11:47:56 +00:00
Daniel Sanders
e019c08bf6 [mips][msa] Added a regression test that depended on multiple patches to pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192961 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-18 09:52:21 +00:00
Daniel Sanders
52244da7f2 [mips][msa] Added lsa instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192895 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-17 13:38:20 +00:00
Daniel Sanders
071aed9422 Fix r192888: test/CodeGen/Mips/msa/3r_ld_st.ll should have been deleted
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192889 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-17 12:36:35 +00:00
Daniel Sanders
62e87cb241 [mips][msa] Added support for build_vector for v4f32 and v2f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 13:14:41 +00:00
Akira Hatanaka
89fee2ff92 [mips] Transfer kill flag to the newly created operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192662 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 01:06:30 +00:00
Reed Kotler
7f0125ba19 For Mips16, start to consolidate all forms of 32 bit literal loading so that
they can be better handled and optimized in the Mips16 constant island code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-12 02:19:08 +00:00
Matheus Almeida
71e7893757 [mips][msa] Improves robustness of the test by enhancing pattern matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 13:18:01 +00:00
Daniel Sanders
a6e253ddd0 [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192438 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 10:50:42 +00:00
Daniel Sanders
4fa2c32220 [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 10:27:32 +00:00
Daniel Sanders
c879eabcc2 [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 10:14:25 +00:00
Daniel Sanders
b9bee10b21 [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 10:00:06 +00:00
Akira Hatanaka
25dafa388a [mips] Do not generate INS/EXT nodes if target does not have support for
ins/ext.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-09 23:36:17 +00:00
Reed Kotler
78f8339f35 Add fabsf to the list of inlined functions; otherwise
Mips16 will try and create a stub for it and this will
result in a link error because that function does not exist in libc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 19:55:01 +00:00
Reed Kotler
b359bda93d Let rotr and bswap be handled by expansion for Mips16 since we don't
have native instructions for this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192207 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 17:32:33 +00:00
Akira Hatanaka
d56cba0b4b [mips] Test case for r192124.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 21:32:57 +00:00
Reed Kotler
42be15fcbe Add Mips16 patterns for sign extend byte and sign extend halfword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 20:46:19 +00:00
Reed Kotler
5404ed811d Support tblockaddr for static compilation in Mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 22:01:40 +00:00
Akira Hatanaka
60ccc3b0ec [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing
instructions in delay slots along with the original branch instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191978 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 20:51:40 +00:00
Daniel Sanders
7f768e0368 [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 10:22:35 +00:00
Manman Ren
aef1b37824 TBAA: remove !tbaa from testing cases when they are not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 18:17:35 +00:00
Akira Hatanaka
6ff59a16a0 [mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out
of loops.

Previously, two consecutive calls to function "func" would result in the
following sequence of instructions:

1. load $16, %got(func)($gp) // load address of lazy-binding stub.
2. move $25, $16
3. jalr $25                  // jump to lazy-binding stub.
4. nop
5. move $25, $16
6. jalr $25                  // jump to lazy-binding stub again.

With this patch, the second call directly jumps to func's address, bypassing
the lazy-binding resolution routine:

1. load $25, %got(func)($gp) // load address of lazy-binding stub.
2. jalr $25                  // jump to lazy-binding stub.
3. nop
4. load $25, %got(func)($gp) // load resolved address of func.
5. jalr $25                  // directly jump to func.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191591 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-28 00:12:32 +00:00
Daniel Sanders
4d835f1cbe [mips][msa] Implemented insert.d intrinsic.
This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 13:36:54 +00:00
Daniel Sanders
9f30d43122 [mips][msa] Implemented fill.d intrinsic.
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 13:20:41 +00:00
Daniel Sanders
e8eafdb676 [mips][msa] Implemented copy_[us].d intrinsic.
This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 13:04:21 +00:00
Daniel Sanders
37469a1329 [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:31:32 +00:00
Daniel Sanders
b4691b495d [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:17:32 +00:00
Daniel Sanders
e1b1a684dd [mips][msa] Added support for MSA registers to copyPhysReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:03:51 +00:00
Daniel Sanders
c8a1fa77a7 [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 11:48:57 +00:00
Daniel Sanders
f1ef27e6e3 [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 10:08:31 +00:00
Daniel Sanders
d2a31a124f [mips][msa] Expand all truncstores and loadexts for MSA as well as DSP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 09:44:59 +00:00
Daniel Sanders
86f309b4d1 [mips][msa] Added missing check in performSRACombine
Reviewers: jacksprat, dsanders

Reviewed By: dsanders

Differential Revision: http://llvm-reviews.chandlerc.com/D1755

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191495 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 09:25:29 +00:00
Reed Kotler
55d016886c Fix a bad typo in the inline assembly code for mips16 pic fp stubs
and make one cosmetic cleanup to make it look the same as gcc
in this area; adjusting test cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191400 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 20:58:50 +00:00
Daniel Sanders
3706eda52c [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191306 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 14:53:25 +00:00
Daniel Sanders
f515964d36 [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191304 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 14:36:12 +00:00
Daniel Sanders
93d995719e [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191302 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 14:20:00 +00:00
Daniel Sanders
7e0df9aa29 [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 14:02:15 +00:00
Daniel Sanders
acfa5a203c [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR.
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp

This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).

There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.

compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 13:33:07 +00:00
Daniel Sanders
ad16ddeb8e [mips][msa] Non-constant BUILD_VECTOR's should be expanded to INSERT_VECTOR_ELT instead of memory operations.
The resulting code is the same length, but doesnt cause memory traffic or latency.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191297 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 13:16:15 +00:00
Daniel Sanders
421dcc5921 [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics)
This covers the case where fmax_a can be used to implement ISD::FABS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191296 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 13:02:08 +00:00
Daniel Sanders
c998bc9843 [mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 12:32:47 +00:00
Daniel Sanders
89d13c1b38 [mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191291 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 12:18:31 +00:00