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Author SHA1 Message Date
Matt Arsenault
8655b1266f Use cast<> for unchecked use 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208627 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 20:42:57 +00:00
Sebastian Pop
d2b27bba87 use nullptr instead of NULL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208622 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 20:11:01 +00:00
Adam Nemet
45fc47013f [Test] Trim unnecessary .c and .cpp from config.suffix in lit.local.cfg 
Tested by comparing make check VERBOSE=1 before and after to make sure
no tests are missed.  (VERBOSE=1 prints the list of tests.)

Only one test :( remains where .cpp is required:

tools/llvm-cov/range_based_for.cpp:// RUN: llvm-cov range_based_for.cpp | FileCheck %s --check-prefix=STDOUT

The topic was discussed in this thread:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140428/214905.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208621 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 19:57:31 +00:00
Louis Gerbarg
9cec62a27f Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb 
The current patterns for REV16 misses mostn __builtin_bswap16() due to
legalization promoting the operands to from load/stores toi32s and then
truncing/extending them. This patch adds new patterns that catch the resultant
DAGs and codegens them to rev16 instructions. Tests included.

rdar://15353652

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208620 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 19:53:52 +00:00
Matt Arsenault
b36e348af3 Use cast<> for unchecked use 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208618 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 19:26:38 +00:00
Matt Arsenault
76aa42c199 Use range for 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208617 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 19:23:21 +00:00
Sebastian Pop
2f5f1c2ccb do not assert when delinearization fails 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208615 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 19:01:53 +00:00
Sebastian Pop
d9673ebd34 use isZero() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208614 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 19:01:49 +00:00
David Blaikie
9f84cecfdc DwarfDebug: Avoid an extra map lookup while constructing abstract scope DIEs and reduce nesting/conditionals. 
One test case had to be updated as it still had the extra indirection
for the variable list - removing the extra indirection got it back to
passing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208608 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 18:23:35 +00:00
Tim Northover
d6cd0381f6 TableGen: use PrintMethods to print more aliases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208607 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 18:04:06 +00:00
Tim Northover
2161fd6114 AArch64/ARM64: use InstAliases for NEON logical (imm) instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208606 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 18:03:42 +00:00
Tim Northover
c56a5421b8 AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen. 
This is a slightly different approach to AArch64 (the base instruction
definitions aren't quite right for that to work), but achieves the
same thing and reduces C++ hackery in AsmParser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208605 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 18:03:36 +00:00
Matt Arsenault
5049ca67c2 R600: Add mul24 intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208604 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 17:49:57 +00:00
Matt Arsenault
621299806c Make SimplifyDemandedBits understand BUILD_PAIR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208598 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 17:14:48 +00:00
Matheus Almeida
db5b7e016a [mips] Move disassembler test (test_2r_msa64) into correct folder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208594 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 16:59:34 +00:00
Matheus Almeida
4d28469a8d [mips] Move disassembler test (Mips MSA test_vec) into correct folder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208592 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 16:31:45 +00:00
Matheus Almeida
d8527e2578 [mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct folder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208590 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 16:26:53 +00:00
Matheus Almeida
e9cd60685b [mips] Move disassembler tests (Mips MSA test_elm*) into correct folder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208589 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 16:23:45 +00:00
Matheus Almeida
e18828fb2b [mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct folder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208588 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 16:20:46 +00:00
Matheus Almeida
f666827156 [mips] Move disassembler test (Mips MSA test_ctrlregs) into correct folder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208587 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 16:16:59 +00:00
Matheus Almeida
86992065e6 [mips] Move disassembler test (Mips MSA test_bit) into correct folder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208586 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 16:10:00 +00:00
Matheus Almeida
5e3662ae95 [mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, test_3rf) into 
correct folder.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208584 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 16:03:20 +00:00
Daniel Sanders
e44de6afea Revert: r208582 - [mips][mips64r6] Add sel.s and sel.d 
Accidentally committed an unreviewed patch. Reverted it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208583 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 15:43:41 +00:00
Daniel Sanders
87010f33a8 [mips][mips64r6] Add sel.s and sel.d 
Summary:
Also use named constants for common opcode fields.

Depends on D3669

Reviewers: jkolek, vmedic, zoran.jovanovic

Differential Revision: http://reviews.llvm.org/D3670

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208582 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 15:39:10 +00:00
James Molloy
05052f660b [ARM64-BE] Correct grammar mistake pointed out by Tobias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208580 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 15:30:31 +00:00
Daniel Sanders
b1b144c65a [mips][mips64r6] Add d?div, d?mod, d?divu, d?modu 
Summary: Depends on D3668

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208579 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 15:24:16 +00:00
James Molloy
85918049ab [ARM64-BE] Add sphinx documentation for the ARM64 NEON implementation. 
There are some interesting decisions based on non-obvious rationale in
the ARM64-BE NEON implementation - decent documentation is definitely required.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208577 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 15:13:39 +00:00
Daniel Sanders
d76eeb1bce [mips][mips64r6] Added mul/mulu/muh/muhu 
Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208576 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 15:12:45 +00:00
Rafael Espindola
64d3ae0c39 Move EmitDwarfAdvanceLineAddr and EmitDwarfAdvanceFrameAddr to the obj streamer. 
This lets us delete the MCAsmStreamer implementation. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208570 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 14:43:25 +00:00
Rafael Espindola
7624b86cfc Pass a MCObjectStreamer instead of a MCStreamer when possible. 
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208569 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 14:40:12 +00:00
Rafael Espindola
6a139d7a29 Pass a MCObjectStreamer instead of a MCStreamer when possible. 
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208567 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 14:28:48 +00:00
Aaron Ballman
03faa833ec Silencing an MSVC warning about not all control paths returning a value (even though the switch is fully covered). No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208565 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 14:22:58 +00:00
Tim Northover
f502ba6e78 ARM64: remove dead validation code from the AsmParser. 
If this code triggers, any immediate has already been validated so it can't
possibly trigger a diagnostic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208564 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 14:13:21 +00:00
Tim Northover
f8c7bd4696 ARM64: merge "extend" and "shift" addressing-mode enums. 
In terms of assembly, these have too much overlap to be neatly modelled as
disjoint classes: in many cases "lsl" is an acceptable alternative to either
"uxtw" or "uxtx".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208563 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 14:13:17 +00:00
Rafael Espindola
23f2d7ae23 Move EH/Debug frame handling to the object streamer. 
Now that the asm streamer doesn't use it, the MCStreamer doesn't need to know
about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208562 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 14:02:44 +00:00
Rafael Espindola
6ec481443b Remove always true argument and unused field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208561 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:47:05 +00:00
Rafael Espindola
e4b9009399 Remove always true argument and field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208559 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:40:49 +00:00
Rafael Espindola
f4a9638884 Remove always true argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208558 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:34:25 +00:00
Rafael Espindola
044302d718 Remove an always true argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208557 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:30:10 +00:00
Rafael Espindola
2e087f383e Remove write only field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208555 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:20:37 +00:00
Rafael Espindola
6878deac93 Remove now empty method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208554 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:18:13 +00:00
Rafael Espindola
1468683d6a Remove the always true UseCFI member. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208553 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:12:22 +00:00
Benjamin Kramer
b31a977c9c X86: Make sure that we have SSE4.1 before we generate insertps nodes. 
PR19721.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208552 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:12:08 +00:00
Rafael Espindola
cdf5f98f6f Remove the useCFI constructor argument to MCAsmStreamer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208551 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:07:11 +00:00
Daniel Sanders
b6569388b9 [mips] Marked up instructions added in MIPS32 and tested that IAS for -mcpu=mips2 does not accept them 
Summary:
To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are explicitly tested.

Depends on D3695

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3696

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208549 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:04:32 +00:00
Rafael Espindola
7b6f59e8f6 Remove MCUseCFI from TargetMachine. 
It was always true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208547 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 13:01:42 +00:00
Daniel Sanders
31546cd352 [mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them 
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-V that was available in MIPS32R2

Most of these instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now. It happens
because many of the MIPS V instructions have not been implemented.

Depends on D3694

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208546 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 12:52:44 +00:00
Daniel Sanders
b396af3752 [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64 
Summary:
DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no
effect on the CodeGen tests since expansion of i64 prevented their use
anyway.

The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as
well. This is not a functional change since DCLZ is still prohibited by
being a MIPS64 instruction (MIPS16 is only compatible with MIPS32).

No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3694

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208544 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 12:41:59 +00:00
Daniel Sanders
ea27d2f50b [mips] Fold FeatureSEInReg into FeatureMips32r2 
Summary: No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3693

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208543 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 12:28:15 +00:00
Daniel Sanders
d46b2e219d [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2 
Summary:
dsbh and dshd are not available on Mips32r2. No codegen test changes
required since expansion of i64 prevented the use of these instructions
anyway.

Depends on D3690

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208542 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 12:15:41 +00:00