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Author SHA1 Message Date
Nadav Rotem
898c5e86fb docs: Update the benchmark with updated perf numbers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171149 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 08:32:44 +00:00
Nadav Rotem
d6fb53adb1 On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized 
register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.

PR14657.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171148 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 08:15:45 +00:00
Nadav Rotem
3c22a44400 AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook. 
The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171146 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 07:45:10 +00:00
Craig Topper
068aec586d Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171143 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 07:16:08 +00:00
Nadav Rotem
444b4bf5c8 Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum. 
Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171142 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 06:47:41 +00:00
Craig Topper
d0f28c0958 Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171141 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 06:34:54 +00:00
Craig Topper
025c5de9ba Update tablegen parser to allow defm names to start with #NAME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171140 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 06:32:52 +00:00
Craig Topper
87073aad8f Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171137 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 03:35:44 +00:00
Craig Topper
766cbae4b1 Mark the divide instructions as hasSideEffects=0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171136 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 03:01:18 +00:00
Eric Christopher
64f824c9d1 For the dwarf5 split debug info code split out the string section 
per compile unit/skeleton compile unit. Update tests accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171133 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:14:01 +00:00
Eric Christopher
d84aa00c7c FileCheck-ize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171132 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:13:58 +00:00
Eric Christopher
5211876288 FileCheck-ize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171131 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:13:55 +00:00
Craig Topper
0b9c5e268f Add hasSideEffects=0 to CMP*rr_REV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171130 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:08:46 +00:00
Nadav Rotem
d92ee757c3 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171129 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:04:12 +00:00
Craig Topper
5e6a86c7f0 Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171128 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:01:33 +00:00
Eric Christopher
32b3768ec1 Right now all of the relocations are 32-bit dwarf, and the relocation 
information doesn't return an addend for Rel relocations. Go ahead
and use this information to fix relocation handling inside dwarfdump
for 32-bit ELF REL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171126 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 01:07:07 +00:00
Nadav Rotem
5dd839430c If all of the write objects are identified then we can vectorize the loop even if the read objects are unidentified. 
PR14719.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171124 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 23:30:53 +00:00
Craig Topper
e9fd6ad567 Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171123 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 23:27:57 +00:00
Craig Topper
ee5b63cb52 Add hasSideEffects=0 to some atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 23:08:12 +00:00
Craig Topper
b87a5b3a1f Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171121 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 22:19:23 +00:00
Nick Lewycky
dbf5081a31 80 columns. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171120 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 22:00:49 +00:00
Nick Lewycky
1dec62ed43 Remove mid-optimizer warning. This situation should be handled differently, 
such as by a compiler warning, a check in clang -fsanitizer=undefined, being
optimized to unreachable, or a combination of the above. PR14722.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171119 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 22:00:35 +00:00
Craig Topper
37cb8398c8 Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171118 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:30:22 +00:00
Craig Topper
a85cbfeba7 Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171117 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:04:30 +00:00
Nadav Rotem
8c6cb31f6e Update the docs with the new workload that was added. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171115 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 19:45:00 +00:00
Nadav Rotem
13eb1e7817 LoopVectorizer: Optimize the vectorization of consecutive memory access when the iteration step is -1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171114 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 19:08:17 +00:00
Eli Bendersky
f1a26cf9df Fix comment typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171113 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 18:15:42 +00:00
Evgeniy Stepanov
b53be53c72 [msan] Raise alignment of origin stores/loads when possible. 
Origin alignment is as high as the alignment of the corresponding application
location, but never less than 4.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171110 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 11:55:09 +00:00
Evgeniy Stepanov
ab29644a33 [msan] Expand the file comment with track-origins info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 10:59:00 +00:00
Benjamin Kramer
23c5021f42 Fix quoting in configure. Patch by Krzysztof Parzyszek! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171108 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 10:48:49 +00:00
Craig Topper
0a5ead92ff Merge still more SSE/AVX instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171103 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 07:54:43 +00:00
Craig Topper
07555fc640 Merge more SSE/AVX instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171102 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 07:20:35 +00:00
NAKAMURA Takumi
fc093def2d TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in fieldFromInstruction(). 
Reported by Yang Yongyong, thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171101 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:43:14 +00:00
Nadav Rotem
00ba3014d8 revert an accidental commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171098 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:16:03 +00:00
Craig Topper
755841d9d7 Fix 80 column violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171097 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:15:53 +00:00
Craig Topper
6f9d44e072 Fix class name in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171096 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:15:09 +00:00
Craig Topper
219bc2db1f Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171095 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:14:15 +00:00
Nadav Rotem
f7769e3c2f Doc: add fmuladd to the list of vectorizeable functions. Thanks hfinkel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171094 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:03:35 +00:00
Craig Topper
02082efaab Remove 'v' from mnemonic to fix asm matching failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171093 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:02:15 +00:00
Craig Topper
3cdc3827ce Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 05:49:15 +00:00
Nadav Rotem
a05f7cbbde Reformat the docs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171091 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 04:59:20 +00:00
Nadav Rotem
4595528781 white space 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171090 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 04:58:12 +00:00
Craig Topper
09a326d3f0 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 04:36:03 +00:00
Craig Topper
1fe132ae7d Merge an AVX/SSE 256-bit and 128-bit multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:56:47 +00:00
Craig Topper
b5c590a586 Mark VANDNPD/VANDNPDS as not commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171085 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:48:10 +00:00
NAKAMURA Takumi
b1a3bafbf1 llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171084 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:19:30 +00:00
NAKAMURA Takumi
05c8fd9ee2 llvm/test/CodeGen/X86: Disable avx in two tests corresponding to r171082. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171083 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:08:55 +00:00
Craig Topper
174a3d3e63 Remove alignment from a bunch more VEX encoded operations in the folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171082 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 02:44:47 +00:00
Craig Topper
d83a73adf0 Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171081 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 02:14:19 +00:00
Craig Topper
1ac0046fa8 Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171080 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 01:47:12 +00:00