Evan Cheng
8a0b2daac2
Fix MOVMSKPDrr encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72535 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 18:55:28 +00:00
Evan Cheng
ed7f56b555
Fix PSIGND encoding bug. Patch by Sean Callanan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72534 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 18:48:53 +00:00
Sanjiv Gupta
dd4694b519
Emit debug info for locals with proper scope.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72531 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 18:24:11 +00:00
Sanjiv Gupta
a455942895
Mark the branch insns correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72529 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 17:32:56 +00:00
Sanjiv Gupta
df75a27609
Fixing problems that got exposed after the refactoring of LegalizeDAG done in 72447.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 06:59:57 +00:00
Eli Friedman
c06441e5ea
Return the operand rather than a null SDValue when the given SELECT_CC
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is actually legal. Part of LegalizeDAG cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72513 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 04:31:08 +00:00
Jeffrey Yasskin
2d92c71668
This patch brings the list of attributes in CPPBackend.cpp up to date with the
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list in Attributes.h. It also reorders the CPPBackend list to match so that
it's easier to see that it's complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72510 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 03:16:17 +00:00
Bill Wendling
3b1259bb9f
"The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but
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the Intel manual (screenshot) says it should be 0b11110110 (f6). The existing
encoding causes a disassembly conflict with MMX_PAVGBrm, which really should be
0f e0."
Patch by Sean Callanan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 02:04:00 +00:00
Evan Cheng
8b944d39b3
Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
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e.g.
orl $65536, 8(%rax)
=>
orb $1, 10(%rax)
Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 00:35:15 +00:00
Eli Friedman
ba2352b066
Ger rid of some dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 20:39:00 +00:00
Evan Cheng
bc9be219d6
Fix sfence jit encoding. Patch by Sean Callanan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72488 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 18:38:01 +00:00
Bruno Cardoso Lopes
d3bdf19ce7
Added support for fround, fextend and FP_TO_SINT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 17:23:44 +00:00
Eli Friedman
36df499648
Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
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FP_TO_XINT. Necessary for some cleanups I'm working on. Updated
from the previous version (r72431) to fix a bug and make some things a
bit clearer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72445 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 00:47:34 +00:00
Daniel Dunbar
82205570d1
Back out r72431, it is causing a number of compilation crashes with clang.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-26 21:27:02 +00:00
Stefanus Du Toit
8cf5ab153d
Update CPU capabilities for AMD machines
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- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72434 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-26 21:04:35 +00:00
Eli Friedman
ecc23a5240
Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
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FP_TO_XINT. Necessary for some cleanups I'm working on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72431 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-26 19:18:56 +00:00
Chris Lattner
d9b77159d6
add some late optimizations that GCC does. It thinks these are a win
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even on Core2, not just AMD processors which was a surprise to me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72396 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-25 20:28:19 +00:00
Chris Lattner
0c85aabfdc
fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72395 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-25 19:51:07 +00:00
Chris Lattner
f9dc644936
we should eventually add -march=atom and the new atom movbe instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72387 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-25 16:34:44 +00:00
Eli Friedman
1a8229b162
Make the PPC backend use a legal type for the operands to the BUILD_VECTOR
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nodes it generates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72356 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-24 02:03:36 +00:00
Eli Friedman
108b519cc1
Make the X86 backend mark EXTRACT_SUBVECTOR as Expand, at least for the
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moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72350 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 22:44:52 +00:00
Anton Korobeynikov
6d7d2aa38a
Add ARMv7 architecture, Cortex processors and different FPU modes handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:51:43 +00:00
Anton Korobeynikov
88ce667003
Emit ARM Build Attributes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72336 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:51:20 +00:00
Anton Korobeynikov
41a024385f
Propagate CPU string out of SubtargetFeatures
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:50:50 +00:00
Eli Friedman
948e95a381
Make the x86 backend custom-lower UINT_TO_FP and FP_TO_UINT on 32-bit
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systems instead of attempting to promote them to a 64-bit SINT_TO_FP or
FP_TO_SINT. This is in preparation for removing the type legalization
code from LegalizeDAG: once type legalization is gone from LegalizeDAG,
it won't be able to handle the i64 operand/result correctly.
This isn't quite ideal, but I don't think any other operation for any
target ends up in this situation, so treating this case specially seems
reasonable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72324 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 09:59:16 +00:00
Oscar Fuentes
a2ac75d547
CMake: Use libpthread in tblgen when needed. Updated list of source
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files for PIC16 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72277 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-22 20:55:15 +00:00
Bob Wilson
2f95461ee2
Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls
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for ARM. This fixes rdar://6908807.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72269 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-22 17:38:41 +00:00
Sanjiv Gupta
a57bc3ba02
Emit debug information for globals (which include automatic variables as well because on PIC16 they are emitted as globals by the frontend).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72262 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-22 13:58:45 +00:00
Bob Wilson
261f2a2337
Minor formatting fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72172 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 16:30:25 +00:00
Evan Cheng
d7f666a869
Try again. Allow call to immediate address for ELF or when in static relocation mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72160 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 04:53:57 +00:00
Evan Cheng
65cdee3fd4
Cannot use immediate as call absolute target in PIC mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72154 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 01:11:00 +00:00
Bob Wilson
6aa219a18c
Fix pr4227: Handle large immediate values in inline assembly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72138 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-19 21:27:57 +00:00
Bob Wilson
86c212e894
Follow up on new support for memory operands in ARM inline assembly.
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This fixes pr4233.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72115 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-19 18:33:02 +00:00
Bob Wilson
04746eae49
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
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the stack. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72106 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-19 10:02:36 +00:00
Bob Wilson
224c244f56
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72105 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-19 05:53:42 +00:00
Dale Johannesen
f4786cc07a
Spacing fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72083 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-19 00:46:42 +00:00
Dale Johannesen
94c9cd17de
Add OpSize to 16-bit ADC and SBB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72045 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-18 21:41:59 +00:00
Bob Wilson
e6abdffe06
Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has
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to run last because it needs to know the exact size and position of every
basic block. Currently CodePlacementOpt is set up to run last. It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-18 20:55:32 +00:00
Dale Johannesen
ca11dae4a4
Fill in the missing patterns for ADC and SBB.
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Some comment cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72022 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-18 17:44:15 +00:00
Anton Korobeynikov
e4fdb8b8ff
Mark rotl/rotr as expand. This generates pretty ugly code, but this is better than nothing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71976 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-17 10:16:28 +00:00
Anton Korobeynikov
aceb620de8
Typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71975 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-17 10:15:22 +00:00
Jakob Stoklund Olesen
b5426457f0
Fix a missing def-flag on a Mips epilogue load.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71935 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-16 07:26:06 +00:00
Jakob Stoklund Olesen
f2c3f6a855
Remember to set def-flag on register loaded from stack slot in CellSPU.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71934 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-16 07:25:44 +00:00
Mike Stump
11adeed8b3
Reflow to fit 80-col.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71813 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-14 23:23:37 +00:00
Mike Stump
6726be6a67
Reflow to fit 80-col.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-14 23:22:47 +00:00
Jim Grosbach
f957012866
Update the names of the exception handling sjlj instrinsics to
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llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71758 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-14 00:46:35 +00:00
Jim Grosbach
6aa7197fb5
Spelling correction s/builting/builtin/ and remove trailing whitespace in a few places
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71735 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 22:32:43 +00:00
Evan Cheng
6ebf7bc740
Run code placement optimization for targets that want it (arm and x86 for now).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:42:09 +00:00
Bill Wendling
587daedce2
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
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booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:33:08 +00:00
Sanjiv Gupta
ad6585b021
Run through the list of globals once and sectionize all types of globlas includeing declarations. Later emit them from their section lists.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71661 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 15:13:17 +00:00