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885 Commits

Author SHA1 Message Date
Craig Topper
3949b8382d Mark several instructions SSE2 instead of SSE3 as they should be. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 06:45:27 +00:00
Benjamin Kramer
c8e340da82 X86: Rename the CLMUL target feature to PCLMUL. 
It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157745 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 14:34:17 +00:00
Craig Topper
0559a2f8ae Add intrinsic for pclmulqdq instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157731 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 04:37:40 +00:00
Benjamin Kramer
1386e9b7b1 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-29 19:05:25 +00:00
Craig Topper
189bce48c7 Remove 256-bit AVX non-temporal store intrinsics. Similar was previously done for 128-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156375 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-08 06:58:15 +00:00
Craig Topper
ef2b8bda02 Fix some issues in the f16c instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156287 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:00:15 +00:00
Craig Topper
5f9cccc509 Add SSE4A MOVNTSS/MOVNTSD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156281 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:36:19 +00:00
Nadav Rotem
7bc9698f3a AVX: Add additional vbroadcast replacement sequences for integers. 
Remove the v2f64 patterns because it does not match any vbroadcast
instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155461 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 18:09:59 +00:00
Nadav Rotem
d1a79136e3 AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructions 
using the pattern (vbroadcast (i32load src)). In some cases, after we generate
this pattern new users are added to the load node, which prevent the selection
of the blend pattern. This commit provides fallback patterns which perform
in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155437 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 11:07:03 +00:00
Elena Demikhovsky
1da5867236 ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155309 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-22 09:39:03 +00:00
Craig Topper
ffa6c40ecf Replace vpermd/vpermps intrinic patterns with custom lowering to target specific nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154801 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 07:13:00 +00:00
Craig Topper
7e9f7fbc11 Flip the arguments when converting vpermd/vpermps intrinsics into instructions. The intrinsic has the mask as the last operand, but the instruction has it as the second. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154797 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 06:26:15 +00:00
Craig Topper
8325c11d47 Merge vpermps/vpermd and vpermpd/vpermq SD nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154782 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 00:41:45 +00:00
Craig Topper
2cb1e9dc7d Remove AVX2 vpermq and vpermpd intrinsics. These can now be handled with normal shuffle vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154778 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 22:43:31 +00:00
Nadav Rotem
f16af0a053 Fix PR12529. The Vxx family of instructions are only supported by AVX. 
Use non-vex instructions for SSE4.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154770 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 19:36:44 +00:00
Elena Demikhovsky
73c504af9d Added VPERM optimization for AVX2 shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 11:18:59 +00:00
Craig Topper
bf596c9c61 Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are integer instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154580 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 07:23:00 +00:00
Nadav Rotem
e611378a6e Reapply 154396 after fixing a test. 
Original message:
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendV uses a register for the selection while Vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154483 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 06:40:27 +00:00
Eric Christopher
a139051654 Temporarily revert this patch to see if it brings the buildbots back. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154425 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 19:33:16 +00:00
Nadav Rotem
50e64cfe6e Modify the code that lowers shuffles to blends from using blendvXX to vblendXX. 
blendv uses a register for the selection while vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154396 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 14:33:13 +00:00
Craig Topper
b45c969959 Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove patterns for selecting the intrinsic. Similar was already done for avx1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154272 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-07 22:32:29 +00:00
Craig Topper
f16ffb1259 Move vinsertf128 patterns near the instruction definitions. Add AddedComplexity to AVX2 vextracti128 patterns to give them priority over the integer versions of vextractf128 patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154268 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-07 21:57:43 +00:00
Craig Topper
769bbfd951 Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 05:20:24 +00:00
Chad Rosier
1b1fdc0599 [avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to 
vextractf128 with 128-bit mem dest.

Combines

	vextractf128 $0, %ymm0, %xmm0
	vmovaps %xmm0, (%rdi)

to

    vextractf128 $0, %ymm0, (%rdi)

rdar://11082570


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153139 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 21:43:40 +00:00
Chad Rosier
a3bfdf536e [avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to give 
precedence over the VINSERTF128 avx1 patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153114 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 19:45:07 +00:00
Chad Rosier
666da1611a Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153105 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 18:38:33 +00:00
Chad Rosier
36a273a76c [avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove 
whitespace from test case.  No functional change intended.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153103 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 18:24:55 +00:00
Chad Rosier
33e528d44d [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads. 
This results in things such as

	vmovups	16(%rdi), %xmm0
	vinsertf128	$1, %xmm0, %ymm0, %ymm0

to be combined to

    vinsertf128	$1, 16(%rdi), %ymm0, %ymm0

rdar://11076953



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 17:08:51 +00:00
Chad Rosier
38ca0d78a2 [avx] Add patterns for VINSERTF128rm. 
This results in things such as

	vmovaps	-96(%rbx), %xmm1
	vinsertf128	$1, %xmm1, %ymm0, %ymm0

to be combined to
         
	vinsertf128	$1, -96(%rbx), %ymm0, %ymm0

rdar://10643481

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152762 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 00:45:30 +00:00
Kay Tiong Khoo
5a08cf4d34 *fix typo in comment; test of commit access 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152507 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-10 21:29:49 +00:00
Chad Rosier
abd6674166 Fix a regression from r147481. 
Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.

Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 02:00:48 +00:00
Preston Gurd
e879cbae7c This patch adds instruction latencies for the SSE instructions 
to the instruction scheduler for the Intel Atom.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151590 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-27 23:35:03 +00:00
Pete Cooper
d18134f116 Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151342 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-24 03:51:49 +00:00
Jia Liu
44de83a7f6 some comment fix for X86 and ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 02:03:36 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Craig Topper
6e94e68b75 Remove the last of the old vector_shuffle patterns from X86 isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150795 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 07:02:34 +00:00
Craig Topper
233a64846e Move old movl vector_shuffle patterns. Not needed anymore since vector_shuffles shouldn't reach isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150462 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-14 08:14:53 +00:00
Craig Topper
7505626acd Still more vector_shuffle pattern removal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150365 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 07:23:41 +00:00
Craig Topper
4eaca023dc Remove more vector_shuffle patterns for unpack. These should be target specific nodes when they get to isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150363 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 05:48:49 +00:00
Craig Topper
3b17bf9a7c Recommit r150328. Previous test failures should be fixed by r150360. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150362 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 05:10:10 +00:00
NAKAMURA Takumi
7f42e9886e Revert r150328, "Remove more vector_shuffle patterns." 
It caused 3 failures on pre-penryn and non-x86(generic) hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150357 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 00:10:15 +00:00
Craig Topper
cc9231a05d Remove more vector_shuffle patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150328 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-12 08:14:35 +00:00
Craig Topper
26f927951b Remove more vector_shuffle patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150321 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-12 01:07:34 +00:00
Craig Topper
1f2fa99b2a Remove more vector_shuffle patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150314 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-11 23:31:01 +00:00
Craig Topper
a819c397e7 Remove some patterns for matching vector_shuffle instructions since vector_shuffles should be custom lowered before isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150299 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-11 07:43:35 +00:00
Craig Topper
bc0e4bf754 Remove a couple unneeded intrinsic patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150067 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-08 08:29:30 +00:00
Craig Topper
5a313bb7e8 Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150060 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-08 06:36:57 +00:00
Craig Topper
dbd98a4b1b Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149968 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-07 06:28:42 +00:00
Craig Topper
5b209e84f4 Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 03:14:49 +00:00
Elena Demikhovsky
dcabc7bca9 Optimization for SIGN_EXTEND operation on AVX. 
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 09:10:43 +00:00