Commit Graph

92380 Commits

Author SHA1 Message Date
Bill Wendling
8c18a6fe37 The command line options need to be processed before we create the TargetMachine.
Move the processing of the command line options to right before we create the
TargetMachine instead of after.
<rdar://problem/13468287>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 21:21:50 +00:00
Tim Northover
5a02fc4b5f ARM: implement @llvm.readcyclecounter intrinsic
This implements the @llvm.readcyclecounter intrinsic as the specific
MRC instruction specified in the ARM manuals for CPUs with the Power
Management extensions.

Older CPUs had slightly different methods which may also have to be
implemented eventually, but this should cover all v7 cases.

rdar://problem/13939186

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182603 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 19:11:20 +00:00
Tim Northover
b94a353242 ARM: Add Performance Monitor Extensions feature
Performance monitors, including a basic cycle counter, are an official
extension in the ARMv7 specification. This adds support for enabling and
disabling them, orthogonally from CPU selection.

rdar://problem/13939186

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182602 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 19:11:14 +00:00
Tom Stellard
d078070f6a R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg
Patch by: Vincent Lejeune

https://bugs.freedesktop.org/show_bug.cgi?id=64877

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 18:26:42 +00:00
Benjamin Kramer
5c35290fa3 Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182594 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 17:10:37 +00:00
Jakob Stoklund Olesen
e0b59774cb Fix PR16110: Handle DBG_VALUE in ConnectedVNInfoEqClasses::Distribute().
Now that the LiveDebugVariables pass is running *after* register
coalescing, the ConnectedVNInfoEqClasses class needs to deal with
DBG_VALUE instructions.

This only comes up when rematerialization during coalescing causes the
remaining live range of a virtual register to separate into two
connected components.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 17:02:23 +00:00
Benjamin Kramer
603100d3de More symbols that should be static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182590 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 16:09:15 +00:00
Benjamin Kramer
a32218a7ec Hexagon: Make helper functions static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182588 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 15:43:11 +00:00
Benjamin Kramer
879b071bf5 R600: Hide symbols of implementation details.
Also removes an unused function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 15:43:05 +00:00
Benjamin Kramer
2db14ba90c InlineSpiller: Store bucket pointers instead of iterators.
Lets us use a SetVector instead of an explicit set + vector combination.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182586 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 15:42:57 +00:00
Aaron Ballman
061ff3409d Setting the default value (fixes CRT assertions about uninitialized variable use when doing debug MSVC builds), and fixing coding style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182585 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 14:55:00 +00:00
Rafael Espindola
7eac032203 Fix 32 bit build in c++11 mode.
The error was:
error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing]
        MI.getOperand(6).getImm() & 0x1F,

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182584 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 13:22:30 +00:00
Nick Lewycky
fa03ff99b2 Add missing test from r175092.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182564 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 07:46:13 +00:00
Rafael Espindola
5110102f9f Fix a leak on the r600 backend.
This should bring the valgrind bot back to life.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 03:31:47 +00:00
Rafael Espindola
23e24bd284 clang-format this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182560 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 03:28:39 +00:00
Rafael Espindola
1529f0c718 Remove redundant rpath.
These are not needed since we added the $ORIGIN based rpath.

Fixes pr12517.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182559 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 02:53:22 +00:00
Rafael Espindola
b58484ecd6 Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182558 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 02:38:50 +00:00
Michael Gottesman
e5b97900b2 [objc-arc] Fixed number of prefixing slashes in some comments in a function from 3 to 2 to match the rest of ObjCARCOpts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182557 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 02:35:21 +00:00
Michael Gottesman
a519666423 Fixed trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182556 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 02:03:05 +00:00
Michael Gottesman
cbc8777c58 Updated the comments of APInt.h to match the llvm style guide and be consistent. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182555 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 02:00:03 +00:00
Kevin Enderby
b737702efd Missed removing one of the assert()'s from the LLVMCreateDisasmCPU() library
API with my 176880 revision.  If a bad Triple is passed in it can also assert.
In this case too it should just return 0 to indicate failure to create the
disassembler.

rdar://13955214


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182542 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 00:32:34 +00:00
Chad Rosier
549221f18c Minor fix to comment from my previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182536 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 23:25:59 +00:00
Chad Rosier
6cd0d18f5e Simplify the logic described in the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182534 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 23:23:14 +00:00
David Blaikie
3d33184d9d Solidify the assumption that a DW_TAG_subprogram's type is a DW_TAG_subroutine_type
There were bits & pieces of code lying around that may've given the
impression that debug info metadata supported the possibility that a
subprogram's type could be specified by a non-subroutine type describing
the return type of a void function. This support was incomplete &
unnecessary. Asserts & API have been changed to make the desired usage
more clear.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 23:22:18 +00:00
Chad Rosier
62c320a755 Simplify logic now that r182490 is in place. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182531 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 23:17:36 +00:00
Chad Rosier
b018bab0b8 Simplify logic now that r182490 is in place. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 22:36:55 +00:00
Chad Rosier
5cc3c989fc Simplify logic now that r182490 is in place. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 22:26:05 +00:00
Bill Schmidt
d35da5055b Recognize ValueType operands in source patterns for fast-isel.
Currently the fast-isel table generator recognizes registers, register
classes, and immediates for source pattern operands.  ValueType
operands are not recognized.  This is not a problem for existing
targets with fast-isel support, but will not work for targets like
PowerPC and SPARC that use types in source patterns.

The proposed patch allows ValueType operands and treats them in the
same manner as register classes.  There is no convenient way to map
from a ValueType to a register class, but there's no need to do so.
The table generator already requires that all types in the source
pattern be identical, and we know the register class of the output
operand already.  So we just assign that register class to any
ValueType operands we encounter.

No functional effect on existing targets.  Testing deferred until the
PowerPC target implements fast-isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 20:45:11 +00:00
Bill Schmidt
5cd01f74b1 Change some PowerPC PatLeaf definitions to ImmLeaf for fast-isel.
Using PatLeaf rather than ImmLeaf when defining immediate predicates
prevents simple patterns using those predicates from being recognized
for fast instruction selection.  This patch replaces the immSExt16
PatLeaf predicate with two ImmLeaf predicates, imm32SExt16 and
imm64SExt16, allowing a few more patterns to be recognized (ADDI,
ADDIC, MULLI, ADDI8, and ADDIC8).  Using the new predicates does not
help for LI, LI8, SUBFIC, and SUBFIC8 because these are rejected for
other reasons, but I see no reason to retain the PatLeaf predicate.

No functional change intended, and thus no test cases yet.  This is
preliminary work for enabling fast-isel support for PowerPC.  When
that support is ready, we'll be able to test this function.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 20:09:24 +00:00
Nadav Rotem
3f75c6cfb5 SLPVectorizer: Change the order in which new instructions are added to the function.
We are not working on a DAG and I ran into a number of problems when I enabled the vectorizations of 'diamond-trees' (trees that share leafs).
* Imroved the numbering API.
* Changed the placement of new instructions to the last root.
* Fixed a bug with external tree users with non-zero lane.
* Fixed a bug in the placement of in-tree users.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182508 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 19:47:32 +00:00
Nadav Rotem
23d1d5eb56 X86: Fix a bug in EltsFromConsecutiveLoads. We can't generate new loads without chains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 19:28:41 +00:00
Reid Kleckner
9e8dbe0d2d Remove unneeded call to a base default ctor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182503 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 19:07:26 +00:00
Jean-Luc Duprat
5e6cabd163 This is an update to a previous commit (r181216).
The earlier change list introduced the following inst combines:
B * (uitofp i1 C) —> select C, B, 0
A * (1 - uitofp i1 C) —> select C, 0, A
select C, 0, B + select C, A, 0 —> select C, A, B

Together these 3 changes would simplify :
A * (1 - uitofp i1 C) + B * uitofp i1 C 
down to :
select C, B, A

In practice we found that the first two substitutions can have a
negative effect on performance, because they reduce opportunities to
use FMA contractions; between the two options FMAs are often the
better choice.  This change list amends the previous one to enable
just these inst combines:

select C, B, 0 + select C, 0, A —> select C, B, A
A * (1 - uitofp i1 C) + B * uitofp i1 C —> select C, B, A




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182499 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 18:29:31 +00:00
Rui Ueyama
e0f26bc008 Fix typo in docs/GettingStarted.rst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 18:09:39 +00:00
Adrian Prantl
5da4e4f3b1 Unify formatting of debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182495 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 18:02:19 +00:00
Reid Kleckner
039c56fb57 Fix StringMapIterator compile errors for non-MSVC compilers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 17:32:15 +00:00
Chad Rosier
0e1fae4cf2 Add the IncludeSelf parameter to the MCSubRegIterator and MCSuperRegIterator
constructors.  No functional change.
Part of rdar://12906217


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182490 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 17:26:26 +00:00
Reid Kleckner
284ffa3863 [Support] Add StringMap::swap() and a default ctor for iterators
This makes StringMap<> more compatible with std::map<std::string, ...>.

Differential Revision: http://llvm-reviews.chandlerc.com/D842

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182487 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 17:10:11 +00:00
Benjamin Kramer
60ef6c9295 X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned.
Take #2 on fixing PR15977.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182486 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 17:01:12 +00:00
Arnold Schwaighofer
6e4a9c14f6 LoopVectorize: Make Value pointers that could be RAUW'ed a VH
The Value pointers we store in the induction variable list can be RAUW'ed by a
call to SCEVExpander::expandCodeFor, use a TrackingVH instead. Do the same thing
in some other places where we store pointers that could potentially be RAUW'ed.

Fixes PR16073.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182485 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 16:54:56 +00:00
Rafael Espindola
812789dd3d Fix use after free (pr16103).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182482 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 15:31:11 +00:00
Rafael Espindola
431c73bc33 Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER.
Fixes a use of uninitialized memory found by asan and valgind.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 14:57:42 +00:00
Richard Sandiford
dbd8eb26ce [SystemZ] Rename PSW to CC
Addresses a review comment from Ulrich Weigand.  No functional change intended.

I'm not sure whether the old TODO that this patch touches still holds,
but that's something we'd get to when adding a targetted scheduling
description.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 13:38:45 +00:00
Rafael Espindola
d34c40514e sync projects/sample's autohell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 12:37:27 +00:00
Richard Sandiford
487399a60f [SystemZ] Fix thinko in long branch pass
The original version of the pass could underestimate the length of a backward
branch in cases like:

    alignment to N bytes or more
    ...
    relaxable branch A
    ...
 foo: (aligned to M<N bytes)
    ...
 bar: (aligned to N bytes)
    ...
    relaxable branch B to foo

We don't add any misalignment gap for "bar" because N bytes of alignment
had already been reached earlier in the function.  In this case, assuming
that A is relaxed can push "foo" closer to "bar", and make B appear to be
in range.  Similar problems can occur for forward branches.

I don't think it's possible to create blocks with mixed alignments as
things stand, not least because we haven't yet defined getPrefLoopAlignment()
for SystemZ (that would need benchmarking).  So I don't think we can test
this yet.

Thanks to Rafael Espíndola for spotting the bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 09:57:57 +00:00
David Majnemer
3b4b5367da X86: Remove test instructions proceeding shift by immediate instructions
Allow LLVM to take advantage of shift instructions that set the ZF flag,
making instructions that test the destination superfluous.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182454 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 08:13:02 +00:00
NAKAMURA Takumi
7849728485 R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. Specify namespaces explicitly here.
MSC is confused about "memcpy" between <cstring> and llvm::Intrinsic::memcpy, when llvm::Intrinsic were exposed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182452 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 06:37:31 +00:00
NAKAMURA Takumi
51c2e124e3 R600: Whitespace and untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 06:37:25 +00:00
Owen Anderson
f9c3ea31db Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182450 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 06:36:09 +00:00
Filip Pizlo
6cfed36338 Expose the RTDyldMemoryManager through the C API. This allows clients of
the C API to provide their own way of allocating JIT memory (both code 
and data) and finalizing memory permissions (page protections, cache 
flush).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182448 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 02:46:43 +00:00