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8d4de5abfa
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260 Commits

Author SHA1 Message Date
Bob Wilson
8d4de5abfa Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 18:26:41 +00:00
Bob Wilson
04ea6e5150 Add an indirect branch pattern for ARM. Testcase will be coming soon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85355 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 00:37:03 +00:00
Johnny Chen
90d7dcfdd9 Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85299 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 20:51:49 +00:00
Johnny Chen
eadeffb306 Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between 
BL_pred and BLr9_pred.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85297 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 20:45:15 +00:00
Bob Wilson
f3b0d1a555 Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" 
instruction format that already takes care of setting this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85280 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 19:52:03 +00:00
Johnny Chen
76b39e88e4 Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85271 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 18:44:24 +00:00
Evan Cheng
162e30921d Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85178 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 23:45:59 +00:00
Bob Wilson
dda9583e51 Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85173 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:59:12 +00:00
Bob Wilson
7e053bb33c Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85167 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:34:44 +00:00
Jim Grosbach
65b7f3af76 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 20:44:34 +00:00
Evan Cheng
2095659a85 Match more patterns to movt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 08:15:52 +00:00
Chris Lattner
017d9478d5 implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84573 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:40:56 +00:00
Bob Wilson
8e86b5195b Set instruction encoding bits 4 and 7 for ARM register-register and 
register-shifted-register instructions.  Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84124 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 19:00:24 +00:00
Sandeep Patel
47eedaa8fa Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 18:59:48 +00:00
Bob Wilson
5361cd2c7d Add some ARM instruction encoding bits. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83983 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 17:35:30 +00:00
Bob Wilson
a7fcb9b840 Fix a tab. Thanks to Johnny Chen for pointing it out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83973 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 15:27:23 +00:00
Dan Gohman
59ac57153b Mark the LDR instruction with isReMaterializable, as it is rematerializable 
when loading from an invariant memory location.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83688 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 23:28:27 +00:00
Bob Wilson
a3e8bf8412 Fix a comment typo. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 20:18:46 +00:00
Evan Cheng
0d92f5f768 Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 08:22:27 +00:00
Evan Cheng
d20d658675 Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 01:33:39 +00:00
Jim Grosbach
c732adf3a1 Add "isBarrier = 1" to return instructions. 
Patch by Sylvere Teissier.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83135 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 01:35:11 +00:00
Evan Cheng
5adb66a646 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo 
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82982 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-28 09:14:39 +00:00
Anton Korobeynikov
b0d8d78138 Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument. 
Disable rematting of it for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82975 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-28 07:26:46 +00:00
Anton Korobeynikov
6a2fa325c1 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. 
This should be better than single load from constpool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-27 23:52:58 +00:00
Evan Cheng
7995ef3b18 Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81310 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-09 01:47:07 +00:00
David Goodwin
e8d82c0e4f Calls clobber FPSCR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80956 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-03 22:12:28 +00:00
David Goodwin
ca01a8d4ab RRX reads CPSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80699 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-01 18:32:09 +00:00
Evan Cheng
d17479e845 Print a nl before pic labels so they start at a new line. This makes assembly more readable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80350 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-28 06:59:37 +00:00
Misha Brukman
bf16f1ddc4 STRD and LDRD require ARMv5TE, not just ARMv5T. 
See http://llvm.org/PR4687 for more info and links.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80244 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-27 14:14:21 +00:00
Bob Wilson
4f38b383d5 Rename ARM "lane_cst" operands to "nohash_imm" since they are used for 
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 21:58:55 +00:00
David Goodwin
5d598aaf3d Update Cortex-A8 instruction itineraries for integer instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-19 18:00:44 +00:00
Jim Grosbach
f35d21617e Add missing defs of R2 and D1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78918 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 16:59:44 +00:00
David Goodwin
6d3d9c3fc3 Finalize itineraries for cortex-a8 integer multiply 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 15:51:13 +00:00
Jim Grosbach
8db5cce021 Remove unnecessary newline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78905 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 15:12:16 +00:00
Jim Grosbach
1add659b0a Correct comment wording 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78904 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 15:11:43 +00:00
David Goodwin
1a8f36e3ce Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 18:31:53 +00:00
Jim Grosbach
378756c0f2 register naming cleanup (s/ip/r12/) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78806 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 15:21:13 +00:00
Owen Anderson
825b72b057 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 20:47:22 +00:00
Jim Grosbach
1b747ad8a0 SjLj based exception handling unwinding support. This patch is nasty, brutish 
and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78625 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 00:09:57 +00:00
Owen Anderson
e50ed30282 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 22:56:29 +00:00
Anton Korobeynikov
8e9ece75db Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 23:10:41 +00:00
Anton Korobeynikov
baf31088f1 Use VLDM / VSTM to spill/reload 128-bit Neon registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 13:35:48 +00:00
David Goodwin
8b7d7ade85 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 16:52:47 +00:00
David Goodwin
42a83f2d15 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 17:53:06 +00:00
Evan Cheng
20a2a0aff3 Make sure Thumb2 uses the right call instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77507 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 21:26:42 +00:00
Evan Cheng
0531d04d00 - Fix an obvious copy and paste error. 
- Darwin Thumb2 call clobbers r9.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77500 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 20:10:36 +00:00
Evan Cheng
5657c01949 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 02:18:14 +00:00
Evan Cheng
e7c329bf4b In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:53:24 +00:00
Evan Cheng
66ac53165e Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:33:29 +00:00
Evan Cheng
eadf04992a Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:03:29 +00:00