Commit Graph

109614 Commits

Author SHA1 Message Date
Zoran Jovanovic
8dad1e1e8e [mips][microMIPS] Implement ANDI16 instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221367 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 17:31:00 +00:00
Tilmann Scheller
8e4d0d84a0 [ARM] Remove redundant assignment.
Found by the Clang static analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221366 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 17:28:19 +00:00
Peter Collingbourne
7cc4447ccf [dfsan] Abort at runtime on indirect calls to uninstrumented vararg functions.
We currently have no infrastructure to support these correctly.

This is accomplished by generating a call to a runtime library function that
aborts at runtime in place of the regular wrapper for such functions. Direct
calls are rewritten in the usual way during traversal of the caller's IR.

We also remove the "split-stack" attribute from such wrappers, as the code
generator cannot currently handle split-stack vararg functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221360 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 17:21:00 +00:00
Duncan P. N. Exon Smith
72ced73d45 IR: MDNode => Value: NamedMDNode::addOperand()
Change `NamedMDNode::addOperand()` to take a `Value *` instead of an
`MDNode *`.  This is part of PR21433.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221359 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 17:16:09 +00:00
Tilmann Scheller
33ccf8e66c [ARM] Remove dead code identified by the Clang static analyzer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221358 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 17:10:43 +00:00
Zoran Jovanovic
0f0a134d9d [mips][microMIPS] Mark symbols as microMIPS if necessary
Differential Revision: http://reviews.llvm.org/D6039


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221355 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 16:35:20 +00:00
Zoran Jovanovic
e9b9ca452f Reverted revisions 221351, 221352 and 221353.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221354 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 16:19:59 +00:00
Zoran Jovanovic
e7ec22de06 [mips][microMIPS] Implement CodeGen support for ANDI16 instruction
Differential Revision: http://reviews.llvm.org/D5797


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221353 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 15:54:05 +00:00
Zoran Jovanovic
8cfd4909f0 [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D5933


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221352 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 15:46:53 +00:00
Zoran Jovanovic
7c63a6331f [mips][microMIPS] Implement ANDI16 instruction
Differential Revision: http://reviews.llvm.org/D5163


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221351 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 15:39:41 +00:00
Tom Stellard
8eaed0f63d R600/SI: Change all instruction assembly names to lowercase.
This matches the format produced by the AMD proprietary driver.

//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
   you want to convert to this script as arguments).
//==================================================================//

; This was necessary on my system so that A-Z in sed would match only
; upper case.  I'm not sure why.
export LC_ALL='C'

TEST_FILES="$*"

MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`

for f in $TEST_FILES; do
  # Check that there are SI tests:
  grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
  if [ $? -eq 0 ]; then
    for match in $MATCHES; do
      sed -i -e "s/\([ :]$match\)/\L\1/" $f
    done

    # Try to get check lines with partial instruction names
    sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
  fi
done

sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll

//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//

export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 14:50:53 +00:00
Tom Stellard
1f06060994 R600/SI: Add an extra check line to make test more strict
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221349 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 14:50:34 +00:00
Rafael Espindola
3ee42f6e5f Add a LLVM_BUILD_STATIC option to cmake.
Setting it to true causes all executables to be statically linked.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221345 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 14:03:58 +00:00
Andrea Di Biagio
042bee88f3 [X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks.
This patch improves the folding of vector AND nodes into blend operations for
targets that feature SSE4.1. A vector AND node where one of the operands is
a constant build_vector with elements that are either zero or all-ones can be
converted into a blend.

This allows for example to simplify the following code:

define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) {
  %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1>
  %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0>
  %3 = or <4 x i32> %1, %2
  ret <4 x i32> %3
}

Before this patch llc (-mcpu=corei7) generated:
        andps  LCPI1_0(%rip), %xmm0, %xmm0
        andps  LCPI1_1(%rip), %xmm1, %xmm1
        orps   %xmm1, %xmm0, %xmm0
        retq

With this patch we generate a single 'vpblendw'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221343 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 13:04:14 +00:00
Oliver Stannard
6b418b297a Fix bashism in tests added by r221341
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221342 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 12:40:21 +00:00
Oliver Stannard
382f7d717c [ARM] Honor FeatureD16 in the assembler and disassembler
Some ARM FPUs only have 16 double-precision registers, rather than the
normal 32. LLVM represents this with the D16 target feature. This is
currently used by CodeGen to avoid using high registers when they are
not available, but the assembler and disassembler do not.

I fix this in the assmebler and disassembler rather than the
InstrInfo.td files, as the latter would require a large number of
changes everywhere one of the floating-point instructions is referenced
in the backend. This solution is similar to the one used for
co-processor numbers and MSR masks.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221341 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 12:06:39 +00:00
Craig Topper
04a45948a0 Improve logic that decides if its profitable to commute when some of the virtual registers involved have uses/defs chains connecting them to physical register. Fix up the tests that this change improves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 06:43:02 +00:00
NAKAMURA Takumi
090bd82177 llvm/test/Transforms/GCOVProfiling: Avoid to parse backslashes in MDString. Use %/T instead of %T.
LLVM Parser decodes "\bb" as hex in "C:\bb-win7\buildername\build...", with MDString.

See also, http://llvm.org/docs/LangRef.html#metadata-nodes-and-metadata-strings

This reverts r221270, "Disable 3 tests in llvm/test/Transforms/GCOVProfiling/ for now. Investigating."

FIXME: Please check EC in GCOVProfiler::emitProfileNotes().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221334 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 06:29:05 +00:00
David Majnemer
4787059b2f llvm-readobj: Add support for dumping the DOS header in PE files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221333 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 06:24:35 +00:00
Jiangning Liu
07e1080b89 Revert 220932.
Commit 220932 caused crash when building clang-tblgen on aarch64 debian target,
so it's blocking all daily tests.

The std::call_once implementation in pthread has bug for aarch64 debian.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221331 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 04:44:31 +00:00
Duncan P. N. Exon Smith
84dc1b5c92 IR: Metadata: Remove unnecessary dyn_cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221328 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 01:55:06 +00:00
Matt Arsenault
1e288409dc Fix broken C++ mode comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221327 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 01:36:22 +00:00
David Majnemer
49c14f54b2 InstSimplify: Exact shifts of X by Y are X if X has the lsb set
Exact shifts may not shift out any non-zero bits. Use computeKnownBits
to determine when this occurs and just return the left hand side.

This fixes PR21477.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221325 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 00:59:59 +00:00
Eric Christopher
4cd064b8e8 Add a check for misbehaving -Wcomment from gcc-4.7 and add
-Wno-comment to the compilation flags if so.

Patch by Filipe Cabecinhas, configure regenerated by me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221323 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 00:35:15 +00:00
Tim Northover
cafa378fe0 ARM: try to add extra CS-register whenever stack alignment >= 8.
We currently try to push an even number of registers to preserve 8-byte
alignment during a function's prologue, but only when the stack alignment is
prcisely 8. Many of the reasons for doing it apply also when that alignment > 8
(the extra store is often free, and can save another stack adjustment, though
less frequently for 16-byte stack alignment).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221321 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 00:27:20 +00:00
Tim Northover
1f771b80c0 ARM/Dwarf: correctly align stack before callee-saved VPRs
We were making an attempt to do this by adding an extra callee-saved GPR (so
that there was an even number in the list), but when that failed we went ahead
and pushed anyway.

This had a couple of potential issues:
  + The .cfi directives we emit misplaced dN because they were based on
    PrologEpilogInserter's calculation.
  + Unaligned stores can be less efficient.
  + Unaligned stores can actually fault (likely only an issue in niche cases,
    but possible).

This adds a final explicit stack adjustment if all other options fail, so that
the actual locations of the registers match up with where they should be.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221320 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 00:27:13 +00:00
David Majnemer
3839fd16a1 Analysis: Make isSafeToSpeculativelyExecute fire less for divides
Divides and remainder operations do not behave like other operations
when they are given poison: they turn into undefined behavior.

It's really hard to know if the operands going into a div are or are not
poison.  Because of this, we should only choose to speculate if there
are constant operands which we can easily reason about.

This fixes PR21412.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221318 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 23:49:08 +00:00
Reid Kleckner
11e6e005b7 Revert "[Reassociate] Canonicalize negative constants out of expressions."
This reverts commit r221171.

It performs this invalid transformation:
-  %div.i = urem i64 -1, %add
-  %sub.i = sub i64 -2, %div.i
+  %div.i = urem i64 1, %add
+  %sub.i1 = add i64 %div.i, -2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221317 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 23:42:45 +00:00
Simon Pilgrim
4ad0654bb4 [X86][SSE] Enable commutation for SSE immediate blend instructions
Patch to allow (v)blendps, (v)blendpd, (v)pblendw and vpblendd instructions to be commuted - swaps the src registers and inverts the blend mask.

This is primarily to improve memory folding (see new tests), but it also improves the quality of shuffles (see modified tests).

Differential Revision: http://reviews.llvm.org/D6015



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221313 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 23:25:08 +00:00
Mark Heffernan
ffb62b7e77 Revert earlier change removing setPreservesCFG from instcombine (r221223) and
change LoopSimplifyPass to be !isCFGOnly.  The motivation for the earlier patch
(r221223) was that LoopSimplify is not preserved by instcombine though
setPreservesCFG indicates that it is.  This change fixes the issue
by making setPreservesCFG no longer imply LoopSimplifyPass, and is therefore less
invasive.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221311 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 23:02:09 +00:00
Juergen Ributzka
6612e3aeda [AArch64] Use the correct register class for ORR.
While fixing up the register classes in the machine combiner in a previous
commit I missed one.

This fixes the last one and adds a test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221308 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 22:20:07 +00:00
Rafael Espindola
2ca0328c3b Revert "[mips] Add names and tests for the hardware registers"
This reverts commit r221299.

The tests

    LLVM :: MC/Disassembler/Mips/mips32.txt
    LLVM :: MC/Disassembler/Mips/mips32_le.txt

were failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221307 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 22:15:05 +00:00
David Blaikie
f49ead7098 Provide gmlt-like inline scope information in the skeleton CU to facilitate symbolication without needing the .dwo files
Clang -gsplit-dwarf self-host -O0, binary increases by 0.0005%, -O2,
binary increases by 25%.

A large binary inside Google, split-dwarf, -O0, and other internal flags
(GDB index, etc) increases by 1.8%, optimized build is 35%.

The size impact may be somewhat greater in .o files (I haven't measured
that much - since the linked executable -O0 numbers seemed low enough)
due to relocations. These relocations could be removed if we taught the
llvm-symbolizer to handle indexed addressing in the .o file (GDB can't
cope with this just yet, but GDB won't be reading this info anyway).
Also debug_ranges could be shared between .o and .dwo, though ideally
debug_ranges would get a schema that could used index(+offset)
addressing, and move to the .dwo file, then we'd be back to sharing
addresses in the address pool again.

But for now, these sizes seem small enough to go ahead with this.

Verified that no other DW_TAGs are produced into the .o file other than
subprograms and inlined_subroutines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221306 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 22:12:25 +00:00
David Blaikie
41ebc263a9 Move cross-unit DIE caching to the DwarfFile level, so it doesn't interfere with fission-gmlt data and produce skeleton<>full unit cross referencing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221305 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 22:12:18 +00:00
Rafael Espindola
c326067040 Don't produce relocations for a difference in a section with no symbols.
We were producing a relocation for
----------------
.section foo,bar
La:
Lb:
 .long   La-Lb
--------------

but not for

---------------------
  .section foo,bar
zed:
La:
Lb:
 .long   La-Lb
----------------

This patch handles the case where both fragments are part of the first atom
in a section and there is no corresponding symbol to that atom.

This fixes pr21328.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221304 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 22:10:33 +00:00
Vasileios Kalintiris
1aa0694c03 [mips] Move COP2 & COP3 load/store instructions from MipsInstrFPU.td to MipsInstrInfo.td. NFC.
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5843

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221300 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 21:45:16 +00:00
Vasileios Kalintiris
a7a01d3c98 [mips] Add names and tests for the hardware registers
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5763

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221299 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 21:30:44 +00:00
Andrea Di Biagio
c270e8abbe [X86] Add 'FeatureSlowSHLD' to cpu 'bdver3'. Also explicit set FeatureAVX and FeatureSSE4A for all the bdver* cpus.
This patch adds 'FeatureSlowSHLD' to 'bdver3'.
According to the official AMD optimization guide for amdfam15: "Using
alternative code in place of SHLD achieves lower overall latency and
requires fewer execution resources. The 32-bit and 64-bit forms of
ADD, ADC, SHR, and LEA (except 16-bit form) are DirectPath
instructions, while SHLD is a VectorPath instruction."

This patch also explicitly sets feature AVX and SSE4A for all the bdver*
cpus. This part of the patch is a non-functional change and it is mainly
done for clarity reasons (Both XOP and FMA4 already imply AVX and SSE4A).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221296 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 21:18:09 +00:00
Justin Bogner
d2d9ad0d66 ErrorOr: Be more explicit in the implicit conversion to bool docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221295 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 21:01:48 +00:00
Arnaud A. de Grandmaison
e1bec75134 [PBQP] Callee saved regs should have a higher cost than scratch regs
Registers are not all equal. Some are not allocatable (infinite cost),
some have to be preserved but can be used, and some others are just free
to use.

Ensure there is a cost hierarchy reflecting this fact, so that the
allocator will favor scratch registers over callee-saved registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221293 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 20:51:29 +00:00
Arnaud A. de Grandmaison
8025a39d11 [PBQP] Tweak spill costs and coalescing benefits
This patch improves how the different costs (register, interference, spill
and coalescing) relates together. The assumption is now that:
 - coalescing (or any other "side effect" of reg alloc) is negative, and
   instead of being derived from a spill cost, they use the block
   frequency info.
 - spill costs are in the [MinSpillCost:+inf( range
 - register or interference costs are in [0.0:MinSpillCost( or +inf

The current MinSpillCost is set to 10.0, which is a random value high
enough that the current constraint builders do not need to worry about
when settings costs. It would however be worth adding a normalization
step for register and interference costs as the last step in the
constraint builder chain to ensure they are not greater than SpillMinCost
(unless this has some sense for some architectures). This would work well
with the current builder pipeline, where all costs are tweaked relatively
to each others, but could grow above MinSpillCost if the pipeline is
deep enough.

The current heuristic is tuned to depend rather on the number of uses of
a live interval rather than a density of uses, as used by the greedy
allocator. This heuristic provides a few percent improvement on a number
of benchmarks (eembc, spec, ...) and will definitely need to change once
spill placement is implemented: the current spill placement is really
ineficient, so making the cost proportionnal to the number of use is a
clear win.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 20:51:24 +00:00
Matt Arsenault
e2463284fc R600/SI: Rename div_scale dest operands to match documentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221291 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 20:29:20 +00:00
Benjamin Kramer
4844826c15 AArch64: Pattern match integer vector abs like we do on ARM.
This kind of pattern is emitted by the loop vectorizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221289 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 20:10:06 +00:00
Kostya Serebryany
c45da43b26 [asan] [mips] changed ShadowOffset32 for systems having 16kb PageSize; patch by Kumar Sukhani
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221288 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 19:46:15 +00:00
Rafael Espindola
d21956e2ec Remove unused DisableRedZone option.
Patch by Steve King.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221282 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 18:18:52 +00:00
David Majnemer
e756ecfb0c InstSimplify: Fold a hasNoSignedWrap() call into a match() expression
No functionality change intended, it's just a little more concise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 17:47:13 +00:00
David Majnemer
57269b02a8 InstSimplify: Fold a hasNoUnsignedWrap() call into a match() expression
No functionality change intended, it's just a little more concise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221280 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 17:38:50 +00:00
Toma Tabacu
dd3894aa8f [mips] Improve support for the .set mips16/nomips16 assembler directives.
Summary:
Appropriately set/clear the FeatureBit for Mips16 when these assembler directives are used and also emit ".set nomips16" (previously, only ".set mips16" was being emitted).

These improvements allow for better testing of the .cpload/.cprestore assembler directives (which are not supposed to work when Mips16 is enabled).

Test Plan: The test is bare-bones because there are no MC tests for Mips16 instructions (there's only one, which checks that the Mips16 ELF header flag gets set), and that suggests to me that it has not been implemented yet in the IAS.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5462

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221277 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 17:18:07 +00:00
Juergen Ributzka
d0de1a525d [Stackmaps] Make test less fragile. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221276 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 17:11:00 +00:00
Sanjay Patel
0bbad0131a remove function names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221274 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 16:27:42 +00:00