Commit Graph

74 Commits

Author SHA1 Message Date
Kalle Raiskila
56354d48bb Fix a iterator out of bounds error, that triggers rarely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 12:55:18 +00:00
Evan Cheng
3e74d6fdd2 Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:08:43 +00:00
Evan Cheng
c60f9b7523 Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 20:59:42 +00:00
Evan Cheng
59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:57:24 +00:00
Evan Cheng
4db3cffe94 Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 17:57:27 +00:00
Evan Cheng
d5b03f252c Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 21:14:33 +00:00
Evan Cheng
22fee2dff4 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 20:07:07 +00:00
Kalle Raiskila
2d25d247bd Add branch hinting for SPU.
The implemented algorithm is overly simplistic (just speculate all branches are
taken)- this is work in progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 14:08:24 +00:00
Anton Korobeynikov
16c29b5f28 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10 12:39:04 +00:00
Andrew Trick
2da8bc8a5f Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
Jakob Stoklund Olesen
78e6e00922 Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 22:35:46 +00:00
Jakob Stoklund Olesen
600f171486 RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 19:19:13 +00:00
Jakob Stoklund Olesen
377b7b7ca3 Replace copyRegToReg with copyPhysReg for CellSPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 07:31:03 +00:00
Kalle Raiskila
951b229ccf Mark the SPU 'lr' instruction to never have side effects.
This allows the fast regiser allocator to remove redundant 
register moves.
Update a set of tests that depend on the register allocator
to be linear scan. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 15:08:16 +00:00
Stuart Hastings
3bf9125933 Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 22:43:56 +00:00
Kalle Raiskila
2320a44b90 Make SPU backend not assert on jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 11:00:02 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 19:06:44 +00:00
Chris Lattner
c7f3ace20c use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 20:16:16 +00:00
Dale Johannesen
93d6a7e9c2 Teach AnalyzeBranch, RemoveBranch and the branch
folder to be tolerant of debug info following the
branch(es) at the end of a block.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 01:38:09 +00:00
Dan Gohman
864e2efce2 Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05 00:44:40 +00:00
Benjamin Kramer
072a56e37d Remove Streams.h from the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79853 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23 11:52:17 +00:00
Eli Friedman
23ed52752b Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24 07:43:59 +00:00
Torok Edwin
c23197a26f llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-14 16:55:14 +00:00
Torok Edwin
dac237e182 Implement changes from Chris's feedback.
Finish converting lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 20:53:28 +00:00
Evan Cheng
2578ba26e7 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 01:59:31 +00:00
Jakob Stoklund Olesen
f2c3f6a855 Remember to set def-flag on register loaded from stack slot in CellSPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71934 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-16 07:25:44 +00:00
Bill Wendling
587daedce2 Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:33:08 +00:00
Scott Michel
7ea02ffe91 CellSPU:
- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
  to the constant pool when they correspond to SPU's shufb instruction's
  special mask values. This avoids the overhead of performing a shuffle on a
  zero-filled vector just to get the special constant when the memory load
  suffices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17 01:15:45 +00:00
Scott Michel
6e1d1470c2 CellSPU:
Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the
llvm-gcc bootstrap a bit further along.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67048 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-16 18:47:25 +00:00
Dan Gohman
97357614b5 Factor out the code to add a MachineOperand to a MachineInstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 05:45:50 +00:00
Dale Johannesen
01b36e6436 Remove non-DebugLoc versions of BuildMI from Alpha and Cell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64433 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:30:42 +00:00
Dale Johannesen
21b5541814 Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-12 23:08:38 +00:00
Bill Wendling
d1c321a89a Move debug loc info along when the spiller creates new instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-12 00:02:55 +00:00
Evan Cheng
dc54d317e7 Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09 07:14:22 +00:00
Evan Cheng
770bcc7b15 Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:43:24 +00:00
Scott Michel
19c10e658a Untabify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62991 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-26 03:37:41 +00:00
Scott Michel
c9c8b2a804 CellSPU:
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
  selection (SPUISelDAGtoDAG.cpp).

  <rant>DAGCombiner will insert all kinds of 64-bit optimizations after
  operation legalization occurs and now we have to do most of the work that
  instruction selection should be doing twice (once to determine if v2i64
  build_vector can be handled by SelectCode(), which then runs all of the
  predicates a second time to select the necessary instructions.) But,
  CellSPU is a good citizen.</rant>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-26 03:31:40 +00:00
Scott Michel
d1e8d9c0a5 CellSPU:
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-21 04:58:48 +00:00
Evan Cheng
04ee5a1d92 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-20 19:12:24 +00:00
Misha Brukman
93c65c8378 Fix off-by-one error in traversing an array; this fixes a test.
The error was reported by gcc-4.3.0 during compilation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61896 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-07 23:07:29 +00:00
Scott Michel
dd950096b9 CellSPU:
- Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we
  need to ensure that i128 is 16-byte aligned in real life), and 128 zero-
  extends are supported.
- New td file: SPU128InstrInfo.td: this is where all new i128 support should
  be put in the future.
- Continue to hammer on i64 operations and test cases; ensure that the only
  remaining problem will be i64 mul.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61784 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-06 03:36:14 +00:00
Scott Michel
52d0001cfc CellSPU:
- Remove custom lowering for BRCOND
- Add remaining functionality for branches in SPUInstrInfo, such as branch
  condition reversal and load/store folding. Updated BrCond test to reflect
  branch reversal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61597 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-03 00:27:53 +00:00
Scott Michel
9bd7a371cb - Make copyRegToReg use the "LR" assembler synonym for "OR". Makes finding
register copies a little easier to pick out from the output.
- Fix bug 3192.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61591 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-02 20:52:08 +00:00
Scott Michel
02d711b93e - Start moving target-dependent nodes that could be represented by an
instruction sequence and cannot ordinarily be simplified by DAGcombine
  into the various target description files or SPUDAGToDAGISel.cpp.

  This makes some 64-bit operations legal.

- Eliminate target-dependent ISD enums.

- Update tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-30 23:28:25 +00:00
Scott Michel
f0569be4a9 - Remove Tilmann's custom truncate lowering: it completely hosed over
DAGcombine's ability to find reasons to remove truncates when they were not
  needed. Consequently, the CellSPU backend would produce correct, but _really
  slow and horrible_, code.

  Replaced with instruction sequences that do the equivalent truncation in
  SPUInstrInfo.td.

- Re-examine how unaligned loads and stores work. Generated unaligned
  load code has been tested on the CellSPU hardware; see the i32operations.c
  and i64operations.c in CodeGen/CellSPU/useful-harnesses.  (While they may be
  toy test code, it does prove that some real world code does compile
  correctly.)

- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
  fault because i64 ult is not yet implemented.)

- Added i64 eq and neq for setcc and select/setcc; started new instruction
  information file for them in SPU64InstrInfo.td. Additional i64 operations
  should be added to this file and not to SPUInstrInfo.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61447 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-27 04:51:36 +00:00
Scott Michel
aedc637c96 CellSPU:
- Fix bug 3185, with misc other cleanups.
- Needed to implement SPUInstrInfo::InsertBranch(). CAUTION: Not sure what
  gets or needs to get passed to InsertBranch() to insert a conditional
  branch. This will abort for now until a good test case shows up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60811 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-10 00:15:19 +00:00
Dan Gohman
c54baa2d43 Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 18:43:12 +00:00
Scott Michel
9c0c6b2e4a CellSPU:
(a) Fix bgs 3052, 3057
(b) Incorporate Duncan's suggestions re: i1 promotion
(c) Indentation updates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59790 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21 02:56:16 +00:00
Dan Gohman
cbad42cfd1 Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-18 19:49:32 +00:00