Commit Graph

78946 Commits

Author SHA1 Message Date
903456245b Hexagon: Fix a nasty order-of-initialization bug.
Reenable the tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146750 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 19:08:59 +00:00
c104cf2002 In DICompositeType, referenced to derived type is either metadata or null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 17:51:31 +00:00
473f95febe Clarify and fix subprogram description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 17:50:04 +00:00
f5bb45f895 Note ARM constant island alignment in the release notes.
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 16:07:41 +00:00
76f13017fc Adds a JSON parser and a benchmark (json-bench) to catch performance regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 13:09:10 +00:00
db21f4c187 Put the '*' in the right place in the unit test. Forgot to fix up this
bit of style, sorry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 09:37:55 +00:00
a602aec869 Make GCC happy by using makeAraryRef instead of the implicit conversion.
I have no idea why GCC can't cope with the implicit conversion and Clang
can, or whose bug it is. Grr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146732 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 09:36:16 +00:00
d916ce3c8e Add a generic collection of class templates to ADT for building
variadic-like functions in C++98. See the comments in the header file
for a more detailed description of how these work. We plan to use these
extensively in the AST matching library. This code and idea were
originally authored by Zhanyong Wan. I've condensed it using macros
to reduce repeatition and adjusted it to fit better with LLVM's ADT.

Thanks to both David Blaikie and Doug Gregor for the review!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146729 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 08:58:59 +00:00
9646acfccf By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146728 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 08:36:07 +00:00
94438ba538 Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 08:06:31 +00:00
de0cfe81b4 Tweak CMake build on Cygwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146725 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 06:21:08 +00:00
46209476e7 Target/Hexagon: Fix CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 06:21:02 +00:00
1da282764a Avoid a confusing assert for silly options: -unroll-runtime -unroll-count=1.
No need for an explicit test case for an unsupported combination of options.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 02:03:48 +00:00
478a4d997a [asan] add a test for instrumenting globals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 01:28:19 +00:00
ddecfe54a3 ARM NEON aliases for vmovq.f*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 00:12:22 +00:00
fec33444c5 Extract a method. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 00:12:05 +00:00
275dd94afe llvm-config: Fix --targets-built, I changed this to use the registry but wasn't
properly initializing the target infos. I decided it wasn't worth linking them
in for this, so just switched back to using the Makefile variable for now. We
can reconsider later if we ever get pluggable targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146711 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 00:04:43 +00:00
b6744db06f Thumb2 ADR assembly parsing w/o the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146710 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 23:52:17 +00:00
7e840efc23 Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 23:46:18 +00:00
bcf14bbd57 llvm-config: Update help text for removal of "backend" pseudo component.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 23:43:17 +00:00
bb53bbb7d4 build/unittests: Fix llvm-config names for gtest libraries, and bring Makefile
library names in line with those used by CMake.
 - Patch by Johannes Obermayr, with tweaks by me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146706 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 23:35:08 +00:00
028700f544 Move parts of lib/Target that use CodeGen into lib/CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146702 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:58:58 +00:00
2f21e8c5ba Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146700 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:56:53 +00:00
a738da7bd3 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:56:33 +00:00
a4b2b1d8fb [asan] add the name of the module to the description of a global variable. This improves the readability of global-buffer-overflow reports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146698 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:55:55 +00:00
d239ff67f2 Add MCTargetDesc library to Hexagon target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:29:08 +00:00
60d99a5278 ARM NEON VTBL/VTBX assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:27:11 +00:00
b6ff6ec85e Enable proper constant island alignment by default.
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146690 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:14:45 +00:00
c8dd20170e Add missing zmovl AVX patterns which were causing crashes.
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:11:31 +00:00
7bcfc9950b [asan] fix a bug (issue 19) where dlclose and the following mmap caused a false positive. compiler part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146688 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 21:59:03 +00:00
276ed0344c Silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146686 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 21:54:55 +00:00
0aaf4cd9b3 ARM NEON two-register double spaced register list parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146685 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 21:44:33 +00:00
0660cfe3c8 Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146684 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 21:34:44 +00:00
b012eb8cc4 Zap unnecessary semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 21:11:38 +00:00
81fdd7bd6a Set specific target cpu for testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 20:22:34 +00:00
74c86e513b Added test case for r146671.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 19:56:07 +00:00
d4c826f648 Use the proper comparator for set_intersection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 19:26:23 +00:00
a0a251372f Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146671 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 18:57:27 +00:00
0508d047fe Update DebugLoc while merging nodes at -O0.
Patch by Kyriakos Georgiou!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 18:21:18 +00:00
0481143fcf Add a test case to make sure that the nop really does follow the bl on ppc64 elf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 17:59:23 +00:00
9642c57ac5 Virtual table holder field is either metadata or null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 17:55:56 +00:00
7f370b6155 Ensure that the nop that should follow a bl call in PPC64 ELF actually does
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 17:54:01 +00:00
7e56831a68 Synthesize missing register class intersections.
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B.  This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.

In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).

This introduces these synthetic register classes:

ARM:
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    tGPR_and_tcGPR
    hGPR_and_tcGPR

X86:
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR64_NOSP_and_GR64_TC
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_TC
    GR32_NOAX_and_GR32_NOSP
    GR64_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_ABCD_and_GR32_NOAX
    GR64_ABCD_and_GR64_TC
    GR32_NOAX_and_GR32_TC
    GR32_AD_and_GR32_NOAX

Other targets are unaffected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 16:48:55 +00:00
27a7859bf7 Pass optLevel to XCoreDAGToDAGISel.
Patch by Kyriakos Georgiou.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146656 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 15:18:35 +00:00
3ba19b1045 Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 04:52:47 +00:00
adeb0a6e64 Make constant folding for GEPs a bit more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146639 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 04:33:48 +00:00
ca072a3977 Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 02:07:20 +00:00
01d426e0e1 Use SmallVector/assign(), rather than std::vector/push_back().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 01:16:09 +00:00
a860b189e4 Add support for lowering fneg when AVX is enabled.
rdar://10566486


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 01:02:25 +00:00
4e5a1ab10b Added InstCombine for "select cond, ~cond, x" type patterns
These can be reduced to "~cond & x" or "~cond | x"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146624 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 00:56:45 +00:00