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19959 Commits

Author SHA1 Message Date
Bill Wendling
95ce2e9c52 Generate the dispatch table for ARM mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141327 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 22:53:00 +00:00
Bill Wendling
e29fa1df55 Refactor some of the code that sets up the entry block for SjLj EH. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 22:18:16 +00:00
Bill Wendling
5e2cbc1133 Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!) 
Place the immediate to OR into a register so that it works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 21:51:21 +00:00
Bill Wendling
04f15b4f2f * Set the low bit of the return address when we are in thumb mode. 
* Some code cleanup.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 21:29:56 +00:00
Justin Holewinski
9a6eba6203 PTX: Implement signed division 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 20:00:33 +00:00
Craig Topper
7ea16b01fa Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 06:44:41 +00:00
Peter Collingbourne
de8f33c199 Build system infrastructure for multiple tblgens. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 01:51:51 +00:00
Bill Wendling
930193cb55 Add the MBBs before inserting the instructions. Doing it afterwards could lead 
to an infinite loop because of the def-use chains.

Also use a frame load instead of store for the LD instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141263 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 00:53:33 +00:00
Cameron Zwarich
8f8aa815b4 Always merge profitable shifts on A9, not just when they have a single use. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141248 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 23:39:02 +00:00
Cameron Zwarich
d78ebe1e12 Remove a check from ARM shifted operand isel helper methods, which were blocking 
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 23:38:50 +00:00
Bill Wendling
5cbef19a1d Get the proper call site numbers for the landing pads. Also remove a magic 
number (18) for the proper addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 23:28:57 +00:00
Jakob Stoklund Olesen
9bb272c900 Override TRI::getSubClassWithSubReg for X86. 
There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode.  In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141206 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 20:26:33 +00:00
Justin Holewinski
591c1c6754 PTX: Fixup a case where getRegClassFor() should be used instead of custom code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141199 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 18:32:25 +00:00
Akira Hatanaka
42be280a28 Fix assertion string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141197 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 18:17:49 +00:00
Akira Hatanaka
41a796e9cc Make sure candidate for delay slot filler is not a return instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 18:16:09 +00:00
Akira Hatanaka
2f52338f50 Add RA to the set of registers that are defined if instruction is a call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 18:11:44 +00:00
Owen Anderson
2dbb46a0a0 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 17:16:40 +00:00
Duncan Sands
62c607b741 Ensure OpCode is not used uninitialized. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 15:13:13 +00:00
Duncan Sands
72478e6046 Comment out a variable that is only used in commented out code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141183 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 15:12:44 +00:00
Duncan Sands
37f80658b3 Remove a bunch of unused variables in the PTX backend (warned about by gcc-4.6). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 15:11:08 +00:00
NAKAMURA Takumi
4cbc5a1118 MipsDelaySlotFiller.cpp: Appease msvc to specify llvm::next() explicitly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 10:11:02 +00:00
Cameron Zwarich
fb77752253 Add braces around something that throws me for a loop. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141173 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 08:59:10 +00:00
Cameron Zwarich
5ee0262014 There is no point in setting out-parameters for a ComplexPattern function when 
it returns false, at least as far as I could tell by reading the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 08:59:05 +00:00
Craig Topper
41e59c7c34 Change C++ style comments to C style comments in X86 disassembler. Patch from Joe Abbey. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141162 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 03:29:32 +00:00
Akira Hatanaka
176965f46b Insert space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 02:22:49 +00:00
Akira Hatanaka
6e4e64859f Do not examine variadic or implicit operands if instruction is a return (jr). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141157 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 02:21:58 +00:00
Akira Hatanaka
0c419a7c4b Clean up function Filler::delayHasHazard. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 02:18:58 +00:00
Akira Hatanaka
0f0c59a0f8 Remove function Filler::insertCallUses. 
Record the registers used and defined by a call in Filler::insertDefsUses.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 02:04:17 +00:00
Akira Hatanaka
7d8e04d5f1 Clean up Filler::findDelayInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:57:46 +00:00
Akira Hatanaka
53120e0a9f Remove function Filler::isDelayFiller. Check if I is the same instruction that 
filled the last delay slot visited.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:30:09 +00:00
Akira Hatanaka
6f818abbe3 Clean up Filler::runOnMachineBasicBlock. Change interface of 
Filler::findDelayInstr.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141150 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:23:39 +00:00
Akira Hatanaka
98f4d4d2db Define a statistic for the number of slots that were filled with useful 
instructions (instructions that are not NOP).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141149 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:19:13 +00:00
Akira Hatanaka
f2f70c2493 Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true before 
I->getDesc().hasDelaySlot() does.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:15:31 +00:00
Akira Hatanaka
cfc3fb5737 Add comments and move assignment statement. If sawStore is true, sawLoad does 
not have to be set.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141147 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:09:37 +00:00
Akira Hatanaka
6585b51821 Correct description string of enable-mips-delay-filler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:06:57 +00:00
Bill Wendling
bb73468e2b Look at the number of entries in the jump table and jump to a 'trap' block if 
the value exceeds that number.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141143 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 00:39:32 +00:00
Bill Wendling
2a85015313 Checkpoint for SJLJ EH code. 
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141140 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 00:02:33 +00:00
Owen Anderson
2fec6c5ff1 Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 23:26:17 +00:00
Kevin Enderby
9e5887b17e Adding back support for printing operands symbolically to ARM's new disassembler 
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 22:44:48 +00:00
Jakob Stoklund Olesen
01faf432d9 Teach PPCInstrInfo to handle sub-classes. 
This has already been done for most other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141083 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 15:28:47 +00:00
Nadav Rotem
34804c4f47 Set operation actions to legal types only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141075 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 12:05:35 +00:00
Nadav Rotem
e8783096d2 Operations should be custom lowered only if their type is legal. 
Test: CellSPU/v2i32.ll when running with -promote-elements



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 10:03:32 +00:00
Craig Topper
6744a17dcf Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 06:30:42 +00:00
Jim Grosbach
9d39036f62 ARM assembly parsing and encoding for VMOV immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:38:36 +00:00
Jim Grosbach
2a3f19d7e3 Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141043 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:03:26 +00:00
Bill Wendling
ff4216a68a Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 22:44:15 +00:00
Jim Grosbach
68259145d9 ARM parsing/encoding for VCMP/VCMPE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 22:30:24 +00:00
Bill Wendling
f7e4aefd0f Check-pointing the new SjLj EH lowering. 
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:25:38 +00:00
Akira Hatanaka
43e43f7d8b Add support for 64-bit logical NOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:23:18 +00:00
Akira Hatanaka
2d57088ff0 Add support for 64-bit count leading ones and zeros instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:16:50 +00:00