962021bc7f
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
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- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 07:38:55 +00:00
f822e733af
Stop abusing EmitInstrWithCustomInserter for target-dependent
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form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets. Add a new hook instead.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-25 21:33:54 +00:00
c82c20b315
Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-24 04:44:57 +00:00
6e8fd90602
Change TargetData's algorithm for computing defualt vector type
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alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23 19:41:15 +00:00
e3ff9ba40c
Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23 19:03:32 +00:00
2808ccb775
Fix X86ISD::CMP i16 to i32 promotion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23 18:21:16 +00:00
3a1287b470
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
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extraction. This fixes PR5998.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 23:24:18 +00:00
f81eca0ab9
Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
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and into SelectionDAGBuilder and FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 20:46:50 +00:00
07c4e1085d
- It's not safe to promote rotates (at least not trivially).
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- Some code refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 20:19:46 +00:00
c048f1d12c
Modified some assert() msg strings; no other functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 18:37:48 +00:00
e566763b19
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
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optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 03:18:23 +00:00
5528e7bcb1
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:47:12 +00:00
fe5dcbc27d
Trim include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:39:06 +00:00
f0757b0edc
Add more const qualifiers on TargetMachine and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:34:56 +00:00
52d2b0ed00
Thumb instructions which have reglist operands at the end and predicate operands
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before reglist were not properly handled with respect to IT Block. Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:01:19 +00:00
a040fffefb
Handle a displacement location in 64-bit as an RIP-relative displacement. It
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fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:
target triple = "x86_64-apple-darwin"
define double @func(double %a) {
%tmp1 = fmul double %a, 5.000000e-01 ; <double> [#uses=1]
ret double %tmp1
}
define i32 @main() nounwind {
%1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
ret i32 0
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101965 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 00:34:04 +00:00
d6139425f5
teach the x86 address matching stuff to handle
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(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.
This finishes off PR1135. Before we compiled the block to:
to:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
leaq 2(%rdx), %r9
movl %esi, (%rdi,%r9,4)
leaq 1(%rdx), %r9
movl %esi, (%rdi,%r9,4)
addq $3, %rdx
movl %esi, (%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
Now we produce:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
movl %esi, 8(%rdi,%rdx,4)
movl %esi, 4(%rdi,%rdx,4)
movl %esi, 12(%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101958 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 23:18:40 +00:00
7609017dc3
Because of the EMMS problem, right now we have to support
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user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own. This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 22:34:09 +00:00
d6b5d72c0f
Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),
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instead of just asserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 21:29:28 +00:00
ef37e3abb7
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
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transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 17:28:50 +00:00
aa2776e934
teach cellspu how to return i8 and i16 from calls,
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patch by Kalle Raiskila!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 05:36:09 +00:00
d7aba875c1
disable optimizations in this directory for MSVC9. This avoids
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an optimizer infinite loop on the file, PR6866.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 01:11:32 +00:00
3974ade503
Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where
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d==15 is considered illegal. Return false instead of assert().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 01:01:57 +00:00
6d972fd087
Remove the palignr intrinsics now that we lower them to vector shuffles,
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shifts and null vectors. Autoupgrade these to what we'd lower them to.
Add a testcase to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 00:59:54 +00:00
6bcf52f00a
More IT instruction error-handling improvements from fuzzing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101839 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 00:15:41 +00:00
d0f3c46d16
Better error handling of invalid IT mask '0000', instead of just asserting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 23:02:58 +00:00
1f65453d0a
Delete an unnecessary reference to SelectionDAGISel::BB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 22:48:45 +00:00
22e401f5d4
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
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Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed. That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.
Also add a test case for condition field '1111'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 21:19:52 +00:00
4c26e93e89
More progress on promoting i16 operations to i32 for x86. Work in progress.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 19:29:22 +00:00
d6cc53cfe4
Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand
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instructions should have Rd (Inst{11-8}) != 0b1111.
Ref: A6.3 32-bit Thumb instruction encoding
A6.3.11 Data-processing (shifted register)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 17:16:40 +00:00
4b7df442a8
ARM disassembler did not react to recent changes to the NEON instruction table.
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VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 16:20:34 +00:00
d456a47dd3
Add missed part of prev. commit
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 20:41:42 +00:00
928eb49cae
Make processor FUs unique for given itinerary. This extends the limit of 32
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FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 20:31:01 +00:00
34e9d17d1b
fix PR6332, allowing an index of zero into a zero sized array
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even if the element of the array has no size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 19:02:33 +00:00
eef6d78be1
teach the x86 asm parser how to handle segment prefixes
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in memory operands. rdar://7874844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 18:56:34 +00:00
3fb150a902
Fix -Wcast-qual warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 17:42:52 +00:00
89f94926b0
remove a dead variable, PR6856
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 17:28:00 +00:00
0d805c33d1
Add const qualifiers to TargetLoweringObjectFile usage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 16:44:48 +00:00
82d5eaf23e
Use const_cast instead of a C-style cast to cast away const.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101639 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 16:43:55 +00:00
383b5f6b91
Delete now-unnecessary const_casts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101637 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 15:32:28 +00:00
b6f778a8f6
Use cast instead of dyn_cast when assuming success.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101636 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 15:31:16 +00:00
d858e90f03
Use const qualifiers with TargetLowering. This eliminates several
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const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 15:26:15 +00:00
1e93df6f0b
Move per-function state out of TargetLowering subclasses and into
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MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 14:41:14 +00:00
2329d66a9f
Name these stub files consistently with the SPU and PPC targets' conventions.
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Also rename the classes appropriately. The CMake build already used these
names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101631 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 08:50:29 +00:00
65de1b9eb3
a bunch of ssse3 instructions are misencoded to think they have an
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i8 field when they really do not. This fixes rdar://7840289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101629 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 07:38:24 +00:00
e5b51ac770
More work to allow dag combiner to promote 16-bit ops to 32-bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 06:13:15 +00:00
9f3f061d74
Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this
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may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 05:30:19 +00:00
9484689f14
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101581 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 23:52:30 +00:00
551754c495
Revert 101465, it broke internal OpenGL testing.
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Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101579 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 23:37:20 +00:00
de0ade4939
Cast to (uint64_t) instead of relying on the "ul" suffix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 23:30:28 +00:00
