Commit Graph

8558 Commits

Author SHA1 Message Date
Dan Gohman
977a76fbb6 Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 22:28:48 +00:00
Nicolas Geoffray
afe6c2b001 Enable exception handling int JIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47079 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 18:39:37 +00:00
Chris Lattner
a1998d1cba Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47067 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 17:24:14 +00:00
Chris Lattner
9f72d1a730 don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
DAGCombine is now quite good at zapifying them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47053 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 07:35:30 +00:00
Nate Begeman
b5041b3085 readme updates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47051 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 07:06:12 +00:00
Nate Begeman
ba8d51c1d7 Make register scavenging happy by not using a reg (CR0) that isn't defined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47045 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 02:58:33 +00:00
Evan Cheng
a4d16a1f0d commuteInstr() can now commute non-ssa machine instrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 02:46:49 +00:00
Dan Gohman
fd29e0eb06 Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 00:35:47 +00:00
Dale Johannesen
3006c39e3a __DATA not __DATA__ is the right segment name on darwin.
Spotted by Nick Kledzik.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47037 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-12 23:35:09 +00:00
Nate Begeman
bf1caa9854 Remove some dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47036 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-12 22:54:40 +00:00
Nate Begeman
cdd1eeca2c SSE4.1 64b integer insert/extract pattern support
Move formats into the formats file


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47035 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-12 22:51:28 +00:00
Evan Cheng
394d28048c Revert r46916 PPCTargetAsmInfo.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47020 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-12 19:25:12 +00:00
Evan Cheng
9f143ce989 Only using x86-64 rip relative addressing in non-staic mode?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47019 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-12 19:20:46 +00:00
Evan Cheng
add251754c Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47002 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-12 07:59:55 +00:00
Evan Cheng
5ae45caf79 Unbreak various insert_vector_elt and extract_vector_elt tests in presence of SSE4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47001 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-12 07:59:45 +00:00
Nate Begeman
5bb013c34a Stuff noticed while grepping code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46979 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-11 23:47:56 +00:00
Nate Begeman
14d12caf1d Enable SSE4 codegen and pattern matching.
Add some notes to the README.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46949 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-11 04:19:36 +00:00
Nate Begeman
a6ed0aa8ec additional missing feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46948 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-11 04:16:09 +00:00
Nate Begeman
ab5d56c6b9 xmm0 variable blends
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46931 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10 18:47:57 +00:00
Dan Gohman
6f0d024a53 Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10 18:45:23 +00:00
Nick Lewycky
16b0bd6c83 Match GCC's behaviour for these sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46916 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10 00:03:54 +00:00
Nate Begeman
fea2be50b9 memopv16i8 had wrong alignment requirement, would have broken pabsb
pabs{b,w,d} are not two address
fix extract-to-mem sse4 ops
add sse4 vector sign extend nodes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46915 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-09 23:46:37 +00:00
Nate Begeman
1426d52cab Skeleton of insert and extract matching, more to come
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46902 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-09 01:38:08 +00:00
Nate Begeman
b5af3344c1 Tablegen support for insert & extract element matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46901 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-09 01:37:05 +00:00
Evan Cheng
5fd79d0560 It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-08 21:20:40 +00:00
Dale Johannesen
0c191872ab 64-bit (MMX) vectors do not need restrictive alignment.
128-bit vectors need it only when SSE is on.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46890 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-08 19:48:20 +00:00
Dan Gohman
60783304f6 Avoid needlessly casting away const qualifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46877 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-08 03:29:40 +00:00
Evan Cheng
33663fc104 Added missing entries in X86 load / store folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46866 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-08 00:12:56 +00:00
Dan Gohman
3069b87437 Follow Chris' suggestion; change the PseudoSourceValue accessors
to return pointers instead of references, since this is always what
is needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46857 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 18:41:25 +00:00
Dan Gohman
4fdad172de Add SourceValue information for outgoing argument stores on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46854 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 16:28:05 +00:00
Evan Cheng
be3bf42331 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
Evan Cheng
15246738f2 In some cases, e.g. ADD32ri, no transformation is made. Guide against it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46849 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:29:53 +00:00
Dan Gohman
69de1932b3 Re-apply the memory operand changes, with a fix for the static
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46827 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-06 22:27:42 +00:00
Evan Cheng
ebaaa91094 Move to getCALLSEQ_END to ensure CALLSEQ_END node produces a flag. This is consistent with the definition in td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46775 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-05 22:44:06 +00:00
Dale Johannesen
e672af15d6 Implement sseregparm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46764 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-05 20:46:33 +00:00
Nate Begeman
5a804e3e21 Ident mnemonics appropriately
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46746 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-05 08:49:09 +00:00
Evan Cheng
4e3f5a4e9c Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-04 23:06:48 +00:00
Nate Begeman
c451ac0a42 This method should be virtual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46723 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-04 23:04:24 +00:00
Nate Begeman
48a65511d0 Eliminate some redundant code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46720 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-04 21:44:06 +00:00
Nate Begeman
204e84e138 The rest of the SSE4.1 intrinsic patterns that are obvious to me. Getting
Evan's help with the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46697 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-04 06:00:24 +00:00
Nate Begeman
2f6f1c02ca Some more SSE 4.1 intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-04 05:34:34 +00:00
Nate Begeman
63ec90a6a8 SSE 4.1 Intrinsics and detection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
Chris Lattner
3d62d780ab explicitly include Compiler.h instead of getting it from tblgen in the middle of a class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46676 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 05:43:57 +00:00
Chris Lattner
a47b9bcbde don't do ReplaceUses on a result that doesn't exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46673 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 03:20:59 +00:00
Evan Cheng
4eecdeb3fa Get rid of the annoying blank lines before labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46667 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 08:39:46 +00:00
Nick Lewycky
916a9f071f Don't use uninitialized values. Fixes vec_align.ll on X86 Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46666 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 08:29:58 +00:00
Evan Cheng
fcf5d4f456 Unbreak ppc debug support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46665 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 05:06:29 +00:00
Evan Cheng
a844bdeab3 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 04:07:54 +00:00
Evan Cheng
b8033e821d Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46655 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 00:17:00 +00:00
Lauro Ramos Venancio
859efca7f9 CBackend: Implement unaligned load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46646 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-01 21:25:59 +00:00