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1317 Commits

Author SHA1 Message Date
Matt Arsenault
015776f38c Add minnum / maxnum codegen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220342 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-21 23:01:01 +00:00
Matt Arsenault
c68710c02d R600/SI: Add missing parameter to div_fmas intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220338 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-21 22:20:55 +00:00
Matt Arsenault
3605d74d23 R600: Use default GlobalDirective 
The overridden one wasn't inserting a space,
so you would end up with .globalfoo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220329 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-21 21:08:36 +00:00
Rafael Espindola
4af7ead7bd Drop support for an old version of ld64 (from darwin 9). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220310 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-21 18:31:09 +00:00
Matt Arsenault
8287a4b564 R600/SI: Add pattern for bswap 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220304 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-21 16:25:08 +00:00
Rafael Espindola
45968c54e9 Fix a bit of confusion about .set and produce more readable assembly. 
Every target we support has support for assembly that looks like

a = b - c
.long a

What is special about MachO is that the above combination suppresses the
production of a relocation.

With this change we avoid producing the intermediary labels when they don't
add any value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220256 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-21 01:17:30 +00:00
Aaron Watry
4e00650f58 R600/SI: Add global atomicrmw xchg 
v2: Add separate offset/no-offset tests

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220110 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 23:33:03 +00:00
Aaron Watry
2107be5bc7 R600/SI: Add global atomicrmw xor 
v2: Add separate offset/no-offset tests

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220109 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 23:33:01 +00:00
Aaron Watry
e81b68b86c R600/SI: Add global atomicrmw or 
v2: Add separate offset/no-offset tests

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220108 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 23:32:59 +00:00
Aaron Watry
1883b51d2e R600/SI: Add global atomicrmw min/umin 
v2: Add separate offset/no-offset tests

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220107 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 23:32:57 +00:00
Aaron Watry
387e397ecd R600/SI: Add global atomicrmw max/umax 
v2: Add separate offset/no-offset tests

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220106 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 23:32:56 +00:00
Aaron Watry
beac0c1403 R600/SI: Add global atomicrmw and 
v2: Add separate offset/no-offset tests

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220105 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 23:32:54 +00:00
Aaron Watry
892bb7df98 R600/SI: Add global atomicrmw sub 
v2: Add separate offset/no-offset tests

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220104 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 23:32:52 +00:00
Matt Arsenault
24463c7df7 R600/SI: Remove redundant setting of instruction bits 
These are all set on the instruction base classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220091 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 21:13:11 +00:00
Matt Arsenault
b6591042cd Fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220068 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 18:02:31 +00:00
Matt Arsenault
0e974f694b R600/SI: Also check for FPImm literal constants 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220067 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 18:00:50 +00:00
Matt Arsenault
7d8f1710a3 R600/SI: Allow commuting with source modifiers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220066 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 18:00:48 +00:00
Matt Arsenault
b4fe2b433e R600/SI: Simplify code with hasModifiersSet 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220065 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 18:00:45 +00:00
Matt Arsenault
415789c57e R600/SI: Fix general commuting breaking src mods 
The generic code trying to use findCommutedOpIndices won't
understand that it needs to swap the modifier operands also,
so it should fail if they are set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220064 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 18:00:43 +00:00
Matt Arsenault
bf5be3f989 R600/SI: Cleanup code with ChangeToFPImmediate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220063 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 18:00:41 +00:00
Matt Arsenault
84895bd2e6 R600/SI: Allow comuting fp immediates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220062 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 18:00:39 +00:00
Matt Arsenault
7eeaefa0c8 R600/SI: Use early return instead of checking condition twice 
Any commutable instruction will have at least src1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220061 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 18:00:37 +00:00
Matt Arsenault
aa796b99bb R600/SI: Use complex pattern for MUBUF load patterns. 
This eliminates a use of the SI_ADDR64_RSRC pseudo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220057 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 17:43:00 +00:00
Matt Arsenault
46b53c9e4b R600/SI: Remove SI_BUFFER_RSRC pseudo 
Just use REG_SEQUENCE directly, so there are fewer
instructions to need to deal with later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220056 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 17:42:56 +00:00
Matt Arsenault
a383742439 R600/SI: Simplify debug printing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219999 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-17 00:36:20 +00:00
Matt Arsenault
61bf4bf2c3 R600/SI: Remove another VALU pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219988 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-16 23:33:37 +00:00
Matt Arsenault
ceb4f4907d R600/SI: Remove unnecessary VALU patterns 
These haven't been necessary since allowing
selecting SALU instructions in non-entry blocks
was enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219956 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-16 20:31:50 +00:00
Matt Arsenault
0134a9bed3 R600: Fix nonsensical implementation of computeKnownBits for BFE 
This was resulting in invalid simplifications of sdiv

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219953 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-16 20:07:40 +00:00
Matt Arsenault
231a8d6cfb R600: Remove dead function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219879 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-16 00:08:09 +00:00
Matt Arsenault
37e484b5ef R600: Remove unnecessary part of computeKnownBitsForTargetNode 
Zero-width BFEs are combined away already, so there's no point in
handling them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219868 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-15 23:37:49 +00:00
Matt Arsenault
bb402de0c9 Move variable down to use 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219867 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-15 23:37:42 +00:00
Tom Stellard
d3fc10a525 R600/SI: Fix bug where immediates were being used in DS addr operands 
The SelectDS1Addr1Offset complex pattern always tries to store constant
lds pointers in the offset operand and store a zero value in the addr operand.
Since the addr operand does not accept immediates, the zero value
needs to first be copied to a register.

This newly created zero value will not go through normal instruction
selection, so we need to manually insert a V_MOV_B32_e32 in the complex
pattern.

This bug was hidden by the fact that if there was another zero value
in the DAG that had not been selected yet, then the CSE done by the DAG
would use the unselected node for the addr operand rather than the one
that was just created.  This would lead to the zero value being selected
and the DAG automatically inserting a V_MOV_B32_e32 instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219848 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-15 21:08:59 +00:00
Matt Arsenault
8b3a9205b7 R600/SI: Also try to use 0 base for misaligned 8-byte DS loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219823 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-15 18:06:43 +00:00
Matt Arsenault
7fdd553b66 R600: Fix miscompiles when BFE has multiple uses 
SimplifyDemandedBits would break the other uses of the operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219819 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-15 17:58:34 +00:00
Rafael Espindola
90ce9f70e2 Simplify handling of --noexecstack by using getNonexecutableStackSection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219799 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-15 16:12:52 +00:00
Rafael Espindola
b510f8d08c Move getNonexecutableStackSection up to the base ELF class. 
The .note.GNU-stack section is not SystemZ/X86 specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219796 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-15 15:44:16 +00:00
Matt Arsenault
18ed4acf21 R600: Use existing variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219778 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-15 05:07:00 +00:00
Matt Arsenault
8a55ca3c41 R600: Remove outdated comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219777 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-15 05:06:57 +00:00
Jan Vesely
d6315ea5a5 Reapply "R600: Add new intrinsic to read work dimensions" 
This effectively reverts revert 219707. After fixing the test to work with
new function name format and renamed intrinsic.

Reviewed-by: Tom Stellard <tom@stellard.net>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219710 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-14 20:05:26 +00:00
Rafael Espindola
e8e8db7ff6 Revert "R600: Add new intrinsic to read work dimensions" 
This reverts commit r219705.

CodeGen/R600/work-item-intrinsics.ll was failing on linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219707 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-14 18:58:04 +00:00
Jan Vesely
6a529850f3 R600: Add new intrinsic to read work dimensions 
v2: Add SI lowering
    Add test

v3: Place work dimensions after the kernel arguments.
v4: Calculate offset while lowering arguments
v5: rebase
v6: change prefix to AMDGPU

Reviewed-by: Tom Stellard <tom@stellard.net>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219705 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-14 18:52:07 +00:00
Jan Vesely
787e3ca6a4 R600: FMA is VecALU only instruction 
Reviewed-by: Tom Stellard <tom@stellard.net>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219704 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-14 18:52:04 +00:00
Matt Arsenault
704b06ce61 R600/SI: Use DS offsets for constant addresses 
Use 0 as the base address for a constant address, so if
we have a constant address we can save moves and form
read2/write2s.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219698 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-14 17:21:19 +00:00
Matt Arsenault
162415e8db R600/SI: Minor cleanup of function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219616 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-13 15:47:59 +00:00
Matt Arsenault
fc9fda5443 R600/SI: Change how DS offsets are printed 
Match SC by using offset/offset0/offset1 and printing
in decimal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219537 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 22:16:07 +00:00
Matt Arsenault
9bd1daf4b9 R600/SI: Match read2/write2 stride 64 versions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219536 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 22:12:32 +00:00
Matt Arsenault
968e1f2f5b R600/SI: Add load / store machine optimizer pass. 
Currently this only functions to match simple cases
where ds_read2_* / ds_write2_* instructions can be used.

In the future it might match some of the other weird
load patterns, such as direct to LDS loads.

Currently enabled only with a subtarget feature to enable
easier testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219533 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 22:01:59 +00:00
Matt Arsenault
b144f27c8f R600/SI: Disable copying of SCC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219519 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-10 17:44:47 +00:00
Matt Arsenault
2e3ee4ceb5 Fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219429 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-09 19:15:15 +00:00
Tom Stellard
a8b2e6f4af R600/SI: Legalize CopyToReg during instruction selection 
The instruction emitter will crash if it encounters a CopyToReg
node with a non-register operand like FrameIndex.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219428 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-09 19:06:00 +00:00