Commit Graph

13692 Commits

Author SHA1 Message Date
Jim Grosbach 6f9f884502 ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:59:38 +00:00
Bruno Cardoso Lopes 53c95880f0 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:28:55 +00:00
Jim Grosbach 14ab1c3387 ARM parsing and encoding tests for CMN/CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:26:58 +00:00
Jim Grosbach d986bc66bc Shuffle ARM assembly tests a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:19:10 +00:00
Jim Grosbach 83ab070fc1 Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes 466b022c99 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:36:51 +00:00
Eli Friedman 2a01946de4 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile.
<rdar://problem/9763308>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:29:53 +00:00
Jim Grosbach 9bb098ad3a Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:14:23 +00:00
Jim Grosbach f333d471d2 Testcases for ARM assembly BX/BXJ instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:25:46 +00:00
Jim Grosbach 37023b05c8 Testcases for ARM assembly BLX/BL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:11:04 +00:00
Jim Grosbach fff76ee7ef Range checking for 16-bit immediates in ARM assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:10:10 +00:00
Evan Cheng 3fd6e755d0 Change test case, one that actually failed before my commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:19:44 +00:00
Jim Grosbach 21101d60ce Add tests for ARM parsing of 'BKPT' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:17:36 +00:00
Jim Grosbach 76cbe02cdd Fix copy-pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:16:30 +00:00
Jim Grosbach e52240c370 Add tests for ARM parsing of 'BIC' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:12:32 +00:00
Jim Grosbach 7ed6d22e96 Add some FIXMEs.
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:10:23 +00:00
Evan Cheng 93a635c82c It's not safe to fold (fptrunc (sqrt (fpext x))) to (sqrtf x) if there is another use of sqrt. rdar://9763193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:08:16 +00:00
Jim Grosbach 59642c2600 Add tests for ARM parsing of 'AND' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 18:55:14 +00:00
Jim Grosbach 19906729a4 Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 18:49:30 +00:00
Jim Grosbach da9f278c74 Add tests for ARM parsing of 'ADD' instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 18:12:46 +00:00
Jim Grosbach 37ee464ea9 Destination register operand is optional for ADC and SBC ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 17:57:17 +00:00
Jim Grosbach e8606dc7c8 Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 17:50:29 +00:00
Bruno Cardoso Lopes 61905f0139 AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 01:15:33 +00:00
Evan Cheng e721f5c8d3 Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 00:42:17 +00:00
Jim Grosbach dc89561fec Add check for predicate w/o S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134987 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 16:25:04 +00:00
Jim Grosbach 92bf81ddd0 Improve test cases from r134746.
Use memory barriers to force if-conversion off for these tests instead of
the internal llc command line option ifcvt-limit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 16:06:01 +00:00
Andrew Trick b9484cafcc Comment correction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134958 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 03:39:22 +00:00
Jim Grosbach 3f00e31706 Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 17:09:57 +00:00
Jim Grosbach 589130fac1 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 16:48:36 +00:00
NAKAMURA Takumi fecdc98390 test/CodeGen/PowerPC/vector.ll: Tweak redirection >%t >%t to >%t >>%t. See also r134814 (test/CodeGen/X86/vector.ll).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 16:21:52 +00:00
Cameron Zwarich ce3a9f51ce Add a missing test for r134882.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 08:35:17 +00:00
Evan Cheng 59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:57:24 +00:00
Rafael Espindola b5a12dd12f Don't duplicate the work done by a gep into a "bitcast" if the gep has
more than one use.

Fixes PR10322.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134883 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:43:47 +00:00
Rafael Espindola aecfdd3068 Move the loads after the calls so that the fix for
PR10292 doesn't show that the loads don't alias
the allocas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 23:53:58 +00:00
Rafael Espindola 4fe509431b Use CHECK-NEXT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 22:56:50 +00:00
Nick Lewycky b4f6095bae Remove tests for APIs that were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 18:55:51 +00:00
Chris Lattner 1afcace3a3 Land the long talked about "type system rewrite" patch. This
patch brings numerous advantages to LLVM.  One way to look at it
is through diffstat:
 109 files changed, 3005 insertions(+), 5906 deletions(-)

Removing almost 3K lines of code is a good thing.  Other advantages
include:

1. Value::getType() is a simple load that can be CSE'd, not a mutating
   union-find operation.
2. Types a uniqued and never move once created, defining away PATypeHolder.
3. Structs can be "named" now, and their name is part of the identity that
   uniques them.  This means that the compiler doesn't merge them structurally
   which makes the IR much less confusing.
4. Now that there is no way to get a cycle in a type graph without a named
   struct type, "upreferences" go away.
5. Type refinement is completely gone, which should make LTO much MUCH faster
   in some common cases with C++ code.
6. Types are now generally immutable, so we can use "Type *" instead 
   "const Type *" everywhere.

Downsides of this patch are that it removes some functions from the C API,
so people using those will have to upgrade to (not yet added) new API.  
"LLVM 3.0" is the right time to do this.

There are still some cleanups pending after this, this patch is large enough
as-is.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 17:41:24 +00:00
Chris Lattner 5445ecdf69 more tests not making the jump into the brave new world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:57:10 +00:00
Chris Lattner ca5470c99d remove some crufy old tests that aren't adding much value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:55:16 +00:00
Chris Lattner 5fe319b3bd remove a test that doesn't make sense in the new world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:52:42 +00:00
NAKAMURA Takumi 9eb36758ac test/CodeGen/X86/vector.ll: Tweak temporary output to appease Win32 hosts.
With Lit (not bash) in a test, multiple redirects >%t might open(%t, "w") multiple. It can be avoided if latter redirect is >>%t.

It might work even if ">/dev/null" were used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 10:22:28 +00:00
Lang Hames f86a547419 Added test cases for GVN signed intrinsics recognition, r134777.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134778 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 00:36:54 +00:00
Jakob Stoklund Olesen 56573cc1ae Hoist spills within a basic block.
Try to move spills as early as possible in their basic block. This can
help eliminate interferences by shortening the live range being
spilled.

This fixes PR10221.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 00:25:03 +00:00
Evan Cheng 3286920505 Add support for ARM / Thumb mode switching with .code 16 and .code 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:36:29 +00:00
Evan Cheng f0b3c12919 Fix broken x86_64 tests which specify non-64-bit cpu's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134756 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:29:33 +00:00
Eli Friedman f06ff4eae3 Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134753 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:16:47 +00:00
Jim Grosbach 25e6d48220 Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:50:04 +00:00
Julien Lerouge f29608267b Add _allrem, _aullrem and _allmul to the runtime for MSVC.
http://llvm.org/bugs/show_bug.cgi?id=10305


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:40:25 +00:00
Cameron Zwarich 33390848a7 Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:39:21 +00:00
Jakob Stoklund Olesen 51458ed09e Be more aggressive about following hints.
RAGreedy::tryAssign will now evict interference from the preferred
register even when another register is free.

To support this, add the EvictionCost struct that counts how many hints
are broken by an eviction. We don't want to break one hint just to
satisfy another.

Rename canEvict to shouldEvict, and add the first bit of eviction policy
that doesn't depend on spill weights: Always make room in the preferred
register as long as the evictees can be split and aren't already
assigned to their preferred register.

Also make the CSR avoidance more accurate. When looking for a cheaper
register it is OK to use a new volatile register. Only CSR aliases that
have never been used before should be avoided.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 20:46:18 +00:00