Commit Graph

4113 Commits

Author SHA1 Message Date
Chris Lattner
387c9dcdda enhance the intrinsic info stuff to emit encodings that don't fit in 32-bits into a
separate side table, using the handy SequenceToOffsetTable class.  This encodes all
these weird things into another 256 bytes, allowing all intrinsics to be encoded this way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156995 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 15:55:41 +00:00
Chris Lattner
d7cf5eb021 finish encoding all of the interesting details of intrinsics. Now intrinsics
are only rejected because they can't be encoded into a 32-bit unit, not because
they contain an unencodable feature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156978 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 05:03:24 +00:00
Chris Lattner
46aaf69e37 strengthen the intrinsic descriptor stuff to be able to handle sin, cos and other
intrinsics that use passed-in arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156977 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 04:30:58 +00:00
Chris Lattner
15706cbf85 simplify code generated by tblgen that is not necessary since we dropped
compatibility with LLVM 2.x bitcode files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 04:07:48 +00:00
Francois Pichet
e4807c1ba1 I forgot the #ifdef _MSC_VER guard in my last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156975 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 04:00:03 +00:00
Francois Pichet
3aca879906 Fix the MSVC 2010 build: disable the optimizer for a problematic function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156973 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 03:38:19 +00:00
Jakob Stoklund Olesen
3778aeb748 Use RegUnits to compute overlapping registers.
TableGen already computes register units as the basic unit of
interference. We can use that to compute the set of overlapping
registers.

This means that we can easily compute overlap sets for one register at a
time. There is no benefit to computing all registers at once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16 23:03:04 +00:00
Chris Lattner
a98aa6ad1e Significantly reduce the compiled size of Functions.cpp by turning a big blob of tblgen
generated code (for Intrinsic::getType) into a table.  This handles common cases right now,
but I plan to extend it to handle all cases and merge in type verification logic as well
in follow-on patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156905 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16 06:34:44 +00:00
Chris Lattner
7200c5cd30 have tblgen emit cast<> instead of dyn_cast<> when we know it must succeed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16 04:51:09 +00:00
Daniel Dunbar
b5cd41e26f llvm-build: Add support for non-installed libraries (e.g., gtest).
- These libraries are only reported by llvm-config when run from a development
   tree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15 18:44:17 +00:00
Daniel Dunbar
177a119621 llvm-build: Don't emit library information for disabled targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15 18:44:12 +00:00
Daniel Dunbar
e1accd7660 [utils] Fix Get{RepositoryPath,SourceVersion} to have a more robust is-git-svn
check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15 18:44:09 +00:00
Jim Grosbach
0ee07e0130 TableGen'erate mapping physical registers to encoding values.
Many targets always use the same bitwise encoding value for physical
registers in all (or most) instructions. Add this mapping to the
.td files and TableGen'erate the information and expose an accessor
in MCRegisterInfo.

patch by Tom Stellard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156829 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15 17:35:57 +00:00
Jakob Stoklund Olesen
40c6fb397d Create a struct representing register units in TableGen.
Besides the weight, we also want to store up to two root registers per
unit. Most units will have a single root, the leaf register they
represent. Units created for ad hoc aliasing get two roots: The two
aliasing registers.

The root registers can be used to compute the set of overlapping
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15 00:50:23 +00:00
Jakob Stoklund Olesen
f402602199 Consider ad hoc aliasing when building RegUnits.
Register units can be used to compute if two registers overlap:

  A overlaps B iff units(A) intersects units(B).

With this change, the above holds true even on targets that use ad hoc
aliasing (currently only ARM). This means that register units can be
used to implement regsOverlap() more efficiently, and the register
allocator can use the concept to model interference.

When there is no ad hoc aliasing, the register units correspond to the
maximal cliques in the register overlap graph. This is optimal, no other
register unit assignment can have fewer units.

With ad hoc aliasing, weird things are possible, and we don't try too
hard to compute the maximal cliques. The current approach is always
correct, and it works very well (probably optimally) as long as the ad
hoc aliasing doesn't have cliques larger than pairs. It seems unlikely
that any target would need more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156763 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14 15:20:39 +00:00
Jakob Stoklund Olesen
31d938a6b1 Record the ad hoc aliasing graph in CodeGenRegister.
The ad hoc aliasing specified in the 'Aliases' list in .td files is
currently only used by computeOverlaps(). It will soon be needed to
build accurate register units as well, so build the undirected graph in
CodeGenRegister::buildObjectGraph() instead.

Aliasing is a symmetric relationship with only one direction specified
in the .td files. Make sure both directions are represented in
getExplicitAliases().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14 15:12:37 +00:00
Jakob Stoklund Olesen
b81cbc271f Compute topological signatures of registers.
TableGen creates new register classes and sub-register indices based on
the sub-register structure present in the register bank. So far, it has
been doing that on a per-register basis, but that is not very efficient.

This patch teaches TableGen to compute topological signatures for
registers, and use that to reduce the amount of redundant computation.
Registers get the same TopoSig if they have identical sub-register
structure.

TopoSigs are not currently exposed outside TableGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14 15:10:07 +00:00
Jakob Stoklund Olesen
ddd657d16d Speed up computeComposites() by using the new SubReg -> SubIdx map.
TableGen doesn't need to search through the SubRegs map to find an
inverse entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156690 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 02:02:26 +00:00
Bill Wendling
9df5ec3984 Remove extraneous ; and the resulting warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 21:56:04 +00:00
Jakob Stoklund Olesen
79e2045531 Defer computation of SuperRegs.
Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156629 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 19:01:01 +00:00
Jakob Stoklund Olesen
fcad79671f Compute secondary sub-registers.
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:

  Q0_Q1 = [Q0, Q1],  Q0 = [D0, D1], Q1 = [D2, D3]

But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.

This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.

This will eventually enable the coalescer to handle copies of skewed
sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:27:10 +00:00
Jakob Stoklund Olesen
148f392195 Precompute lists of explicit sub-registers and indices.
The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 17:46:18 +00:00
Andrew Trick
7b521ad6ee Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.
I initially assumed that the subreg graph was a tree. That may not be true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 00:32:15 +00:00
Jakob Stoklund Olesen
08dc5f2adb Fix warning text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 23:43:30 +00:00
Jakob Stoklund Olesen
ca313e1efa Compute a backwards SubReg -> SubRegIndex map for each register.
This mapping is for internal use by TableGen. It will not be exposed in
the generated files.

Unfortunately, the mapping is not completely well-defined. The X86 xmm
registers appear with multiple sub-register indices in the ymm
registers. This is because of the odd idempotent sub_sd and sub_ss
sub-register indices. I hope to be able to eliminate them entirely, so
we can require the sub-registers to form a tree.

For now, just place the canonical sub_xmm index in the mapping, and
ignore the idempotents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 22:15:00 +00:00
Jakob Stoklund Olesen
da2be82434 Rename getSubRegs() to computeSubRegs().
That's what it does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 22:09:17 +00:00
NAKAMURA Takumi
9fae6ee6af Lit: rewind WinWaitReleased() stuff in TestRunner.
r145222 "lit/TestRunner.py: [Win32] Introduce WinWaitReleased(f), to wait for file handles to be released by children."
r145223 "lit/TestRunner.py: Use RemoveForce()."
r145381 "lit/TestRunner.py: Try to catch ERROR_FILE_NOT_FOUND, too."
r152916 "lit/TestRunner.py: [Win32] Check all opened_files[] released, rather than (obsoleted) written_files[]."
r153172 "lit/TestRunner.py: [Win32] Rework WinWaitReleased() again! "win32file" from Python Win32 Extensions."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156381 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08 14:31:52 +00:00
Preston Gurd
7549354181 Make IntelJITEvents and OProfileJIT as optional libraries and add
optional library support to the llvm-build tool:
 - Add new command line parameter to llvm-build: “--enable-optional-libraries”
 - Add handing of new llvm-build library type “OptionalLibrary”
 - Update Cmake and automake build systems to pass correct flags to llvm-build
   based on configuration

Patch by Dan Malea!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156319 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 19:38:40 +00:00
Jim Grosbach
8e27c96159 TableGen: AsmMatcher diagnostic when missing instruction mnemonic.
Previously, if an instruction definition was missing the mnemonic,
the next line would just assert(). Issue a real diagnostic instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156263 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 17:33:14 +00:00
Jakob Stoklund Olesen
a93090ccd9 Order register classes by spill size first, members last.
This is still a topological ordering such that every register class gets
a smaller enum value than its sub-classes.

Placing the smaller spill sizes first makes a difference for the
super-register class bit masks. When looking for a super-register class,
we usually want the smallest possible kind of super-register. That is
now available as the first bit set in the bit mask.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 23:12:22 +00:00
Jakob Stoklund Olesen
7855ec62c3 Remove TargetRegisterClass::SuperRegClasses.
This manually enumerated list of super-register classes has been
superceeded by the automatically computed super-register class masks
available through SuperRegClassIterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 03:30:28 +00:00
Jakob Stoklund Olesen
dd63a063e2 Use a shared implementation of getMatchingSuperRegClass().
TargetRegisterClass now gives access to the necessary tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 22:49:04 +00:00
Jakob Stoklund Olesen
1a2a19dd3c Add TargetRegisterClass::getSuperRegIndices().
This is a pointer into one of the tables used by
getMatchingSuperRegClass(). It makes it possible to use a shared
implementation of that function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156121 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 22:49:00 +00:00
Jakob Stoklund Olesen
6a0ed18532 Emit SuperRegMasks as part of the existing SubClassMask arrays.
The RC->getSubClassMask() pointer now points to a sequence of register
class bit masks. The first bit mask is the normal sub-class mask. The
following masks are super-reg class masks used by
getMatchingSuperRegClass().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156120 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 22:48:56 +00:00
Jakob Stoklund Olesen
f92be238d6 Compress tables for getMatchingSuperRegClass().
Many register classes only have a few super-registers, so it is not
necessary to keep individual bit masks for all possible sub-register
indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 18:14:20 +00:00
Owen Anderson
5e7469647c Add the half type to the LLVM IR vim syntax highlighting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 17:24:12 +00:00
Jakob Stoklund Olesen
309076ff76 Don't override subreg functions in targets without subregisters.
Some targets have no sub-registers at all. Use the TargetRegisterInfo
versions of composeSubRegIndices(), getSubClassWithSubReg(), and
getMatchingSuperRegClass() for those targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 16:26:20 +00:00
Douglas Gregor
f657da2e48 Move llvm-tblgen's StringMatcher into the TableGen library so it can
be used by clang-tblgen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 17:32:48 +00:00
Craig Topper
8030e1a0df Add ifdef around getSubtargetFeatureName in tablegen output file so that only targets that want the function get it. This prevents other targets from getting an unused function warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 06:56:34 +00:00
Jim Grosbach
14ce6fac24 ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.

rdar://11257547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 22:40:08 +00:00
Craig Topper
f0ae38ef2e Remove 'XXXRegisterClass' from tablegen output. Targets should use '&XXXRegClass' instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-21 01:49:25 +00:00
Andrew Trick
7c0903a924 TableGen'd RegPressure: Added getPressureSetName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 20:44:58 +00:00
Bill Wendling
f4594a3302 Modify the sh-bang to run out-of-the-box for FreeBSDes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 20:31:44 +00:00
Jim Grosbach
c1922c72ad TableGen support for auto-generating assembly two-operand aliases.
Assembly matchers for instructions with a two-operand form. ARM is full
of these, for example:
  add {Rd}, Rn, Rm  // Rd is optional and is the same as Rn if omitted.

The property TwoOperandAliasConstraint on the instruction definition controls
when, and if, an alias will be formed. No explicit InstAlias definitions
are required.

rdar://11255754

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 23:59:23 +00:00
Michael J. Spencer
75338097c7 Remove llvm-ld and llvm-stub (which is only used by llvm-ld).
llvm-ld is no longer useful and causes confusion and so it is being removed.

* Does not work very well on Windows because it must call a gcc like driver to
  assemble and link.
* Has lots of hard coded paths which are wrong on many systems.
* Does not understand most of ld's options.
* Can be partially replaced by llvm-link | opt | {llc | as, llc -filetype=obj} |
  ld, or fully replaced by Clang.

I know of no production use of llvm-ld, and hacking use should be
replaced by Clang's driver.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155147 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 19:27:54 +00:00
Jim Grosbach
b423d18a00 Use a SmallVector instead of std::vector for ResOperands.
There's almost always a small number of instruction operands, so
use a SmallVector and save on heap allocations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 17:52:34 +00:00
Jim Grosbach
8caecdea56 Update some internal naming conventions to modern style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 17:52:32 +00:00
Daniel Dunbar
90275ea2ee llvm-lit: Inject the lit module path at the beginning of sys.path, just in case
the user has another lit somewhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 16:31:08 +00:00
Craig Topper
9b58f29ad0 Make fast isel use &XXXRegClass instead of XXXRegisterClass. Not a functional change since XXXRegisterClass is just a constant alias of &XXXRegClass, but should probably go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 06:52:06 +00:00
Jim Grosbach
d4824fc8aa Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 23:46:25 +00:00