351dc967ba
Added special flag node FLAG.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24934 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-22 02:25:14 +00:00
5c82f4dcdc
add some nodes, forgot to commit this last night :(
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24901 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 16:22:46 +00:00
a5386b0823
Added X86 readport patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24879 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 07:38:38 +00:00
898101c15f
X86 conditional branch support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24870 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-19 23:12:38 +00:00
737f631532
add a node, for completeness
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24819 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-18 07:05:21 +00:00
6aa45292c6
Since extload can also be used by FP, split STDIntExtLoad into two parts,
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one for use with extload, one for use with sextload and zextload, which
are integer only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24814 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-18 02:48:48 +00:00
0b218434cc
add truncstore
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24787 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 20:42:29 +00:00
f5395cee6a
Added source file/line correspondence for dwarf (PowerPC only at this point.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24748 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-16 22:45:29 +00:00
cb17bac3a3
* Promote all 1 bit entities to 8 bit.
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* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24726 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-15 19:49:23 +00:00
543b4583d3
Added constpool, frameindex, and externalsym nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24723 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-15 08:29:48 +00:00
58e84a69f5
Added support to specify predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24715 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 22:02:59 +00:00
2b52426441
Fixed extload type profile. The 4th operand is a ValueType node with type
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OtherVT, it cannot be compare to type of 1st operand which is an integer type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24713 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 19:40:54 +00:00
3d2331dba7
Added sextld + zextld DAG nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24703 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 02:21:01 +00:00
993aeb2ed9
Prepare support for AltiVec multiply, divide, and sqrt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24700 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 22:55:22 +00:00
d2c339cca7
Fix typo :(
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24664 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-11 18:43:13 +00:00
3aed79eadb
add selectcc
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24662 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-11 08:35:54 +00:00
84384546e2
Realize the constant pool & global addrs must always be ptr type
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24660 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-11 07:45:04 +00:00
28a6b02626
Add support for TargetConstantPool nodes to the dag isel emitter, and use
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them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24657 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-10 02:36:00 +00:00
b612ff9569
Use SDTCisPtrTy type property for store address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24656 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-10 01:59:36 +00:00
b51a059b2c
* Added X86 store patterns.
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* Added X86 dec patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24654 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-10 00:48:20 +00:00
d8fe3b3272
Add SDTCisPtrTy and use it for loads, to indicate that the operand of a load
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must be a pointer. This removes a type check out of the code generated by
tblgen for load matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24650 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-09 22:58:42 +00:00
f20da7e1a7
Added support for ComplexPattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24638 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-08 04:28:48 +00:00
68bfd9c1e8
On some targets (e.g. X86), shift amounts are not the same as the value
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being shifted. Don't assume they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24598 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 02:37:26 +00:00
f8ac814957
* Added instruction property hasCtrlDep for those which r/w control-flow
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chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24586 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 08:13:17 +00:00
db40dc2d63
Add globaladdress and targetglobaladdress nodes for dag patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24389 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-17 07:20:15 +00:00
5966955445
add support for SELECT to TargetSelectionDAG.td, add support for
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selecting ints to IA64, and a few other ia64 bits and pieces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24147 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-02 02:37:18 +00:00
e2fd9e2d9d
add support for int->FP and FP->int ops, and add ia64 patterns for these
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24132 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-01 03:07:25 +00:00
1f426deade
Add nodes for CondCodeSDNode and setcc, and add a bunch of pattern fragments
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to make it easy to use them. This lets you write patterns like:
(set PRRC:$rd, (setne GPRC:$rS, imm:$SH))
and stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24009 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-26 17:00:25 +00:00
978982628a
Add undef
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23990 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-25 21:03:14 +00:00
eae6d648da
Use a literal to define ineg instead of immzero
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23851 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-20 23:30:37 +00:00
d684e1a64d
add cttz and ctpop
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23848 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-20 19:38:11 +00:00
444215dddc
add the integer truncate/extension operations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23733 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14 06:40:20 +00:00
13664a6194
add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23726 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14 04:55:10 +00:00
17f2cf05b3
Pull DAG ISel generation nodes out of the PowerPC backend to where they
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can be used by other targets. For those targets that want to use it,
have at. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23680 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-10 06:00:30 +00:00
Evan Cheng
Chris Lattner
Nate Begeman
Jim Laskey
Duraid Madina
Andrew Lenharth