Chris Lattner
a33b93f7f1
sketch out the planned instruction alias mechanism, add some comments about
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how the push/pop mnemonic aliases are wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 18:43:46 +00:00
Duncan Sands
4590766580
Factorize the duplicated logic for choosing the right argument
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calling convention out of the fast and normal ISel files, and
into the calling convention TD file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 13:21:44 +00:00
Duncan Sands
e26032d5b2
Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,
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which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 13:02:38 +00:00
Rafael Espindola
7be2c33193
Add support for files with more than 65280 sections. No testcase since
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it would be a bit too big :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 00:16:26 +00:00
Eric Christopher
76d61478df
Make sure we have a legal type (and simple) before continuing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 21:25:26 +00:00
Chris Lattner
0f899c78e1
Resolve a terrible hack in tblgen: instead of hardcoding
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"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 19:38:20 +00:00
Chris Lattner
693173feef
Implement (and document!) support for MnemonicAlias's to have Requires
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directives, allowing things like this:
def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
Move the rest of the X86 MnemonicAliases over to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117830 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 19:23:13 +00:00
Chris Lattner
a47b265b1a
really zap alias.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:23:25 +00:00
Chris Lattner
b3c417845d
move fcompi alias to .td file and zap some useless code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:22:53 +00:00
Chris Lattner
6f96b0899b
move rep aliases to td file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:17:33 +00:00
Chris Lattner
a17a9a00dc
move sal aliases to .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117821 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:14:54 +00:00
Chris Lattner
1a1ecc9f3c
fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
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for shl. Caught by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:13:10 +00:00
Chris Lattner
8b260a7644
move a bunch more aliases from .cpp -> .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:07:17 +00:00
Chris Lattner
8cb441c9e0
move cmov aliases to .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 17:56:50 +00:00
Chris Lattner
b69fc28e92
move setcc and jcc aliases from .cpp to .td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 17:51:45 +00:00
Chris Lattner
537ca844dd
move some code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 17:38:55 +00:00
Chris Lattner
674c1dcca2
implement (and document!) the first kind of MC assembler alias, which
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just remaps one mnemonic to another. Convert a few of the X86 aliases
from .cpp to .td code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 17:36:36 +00:00
Duncan Sands
aa66099330
Now that the MallocInst no longer exists, this workaround for
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it claiming not to have side-effects is no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 16:12:16 +00:00
Jim Grosbach
7644971232
Add FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 14:54:23 +00:00
Jim Grosbach
604cdf6ea7
Clean up comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 13:48:28 +00:00
Duncan Sands
ad6f541840
If a function does a volatile load from a global constant, do not
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consider it to be readonly. In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment). This fixes PR8279.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117783 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 12:59:44 +00:00
Jim Grosbach
4aaf59d8ed
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 12:59:16 +00:00
Chris Lattner
9a82e70275
stay out of the reserved namespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 04:57:14 +00:00
Chris Lattner
dba34d874d
simplify this code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117771 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 04:35:59 +00:00
Chris Lattner
e5658fa15e
split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 04:09:10 +00:00
Jim Grosbach
4b5236c966
Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 01:40:16 +00:00
Jakob Stoklund Olesen
e5f4e9fb2b
Include MachineBasicBlock numbers in viewCFG() output.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 01:26:19 +00:00
Jakob Stoklund Olesen
5b4bb218d1
Make sure copies are inserted after any exception handling labels at the top of
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a basic block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117764 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 01:26:16 +00:00
Jakob Stoklund Olesen
92095e7b3f
Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is needed
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elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117763 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 01:26:14 +00:00
Jakob Stoklund Olesen
ab56647e6b
Disable more of physical register live intervals verification.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 01:26:11 +00:00
Jakob Stoklund Olesen
7d57753df3
Print out register class of spilled register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 01:26:09 +00:00
Bob Wilson
f74a429816
Overhaul memory barriers in the ARM backend. Radar 8601999.
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There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 00:54:37 +00:00
Jim Grosbach
6b5252db2d
Encode the register list operands for ARM mode LDM/STM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 00:37:59 +00:00
Bill Wendling
52925b60f1
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
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conditional. Check for those instructions explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
Evan Cheng
189c1ec4c1
Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:36:03 +00:00
Jim Grosbach
f38bfd1918
Remove hard tab characters.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:23:15 +00:00
Jim Grosbach
c4bc2111a7
80 column fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:21:57 +00:00
Jim Grosbach
d8a11c25fa
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:21:03 +00:00
Jim Grosbach
0d2d2e9246
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
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encoder functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:19:55 +00:00
Evan Cheng
e09206d4d7
Fix fpscr <-> GPR latency info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117737 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:16:55 +00:00
Rafael Espindola
d179886f05
Be more strict on when we produce an undefined reference. In gas a file with
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just
.type foo,@object
will produce an undefined reference to foo. On the other hand, a file with
just
.weakref bar, foo
will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.
With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.
This is in preparation for a patch implementing .weakref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:09:31 +00:00
Bob Wilson
db1da8ed42
Clean up indentation and other whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117728 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 22:20:45 +00:00
Bob Wilson
09fd64644d
Remove trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 22:20:43 +00:00
Bob Wilson
f0b48f836e
Fix 80-column violation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 22:03:07 +00:00
Bob Wilson
822cb58d08
Change instcombine's getShuffleMask to represent undef with negative values.
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This code had previously used 2*N, where N is the mask length, to represent
undef. That is not safe because the shufflevector operands may have more
than N elements -- they don't have to match the result type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 22:03:05 +00:00
Bob Wilson
46455096be
Remove DAG combiner patch to fold vector splats. Instcombiner does it now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 22:03:02 +00:00
Bob Wilson
4cac5facc3
Make instcombine a little more aggressive in combining vector shuffles.
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Allow splats even if they don't match either of the original shuffles,
possibly due to undef entries in the shuffles masks. Radar 8597790.
Also fix some 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117719 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 22:02:50 +00:00
Jim Grosbach
3df518e67e
add FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:56:51 +00:00
Jim Grosbach
8e0a3eb957
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
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the ARMExpandPseudos pass rather than during the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:35:25 +00:00
Eric Christopher
0e6233bfd7
Handle comparison values we already have - this fixes the consumer-typeset
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failure for llvm-gcc on arm fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:08:19 +00:00