Commit Graph

119606 Commits

Author SHA1 Message Date
Mehdi Amini
a5574d611a Remove DataLayout from TargetLoweringObjectFile, redirect to Module
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11079

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242385 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 06:04:17 +00:00
Mehdi Amini
24e2a7c43f Redirect pointerSize query to the TargetMachine in ASMPrinter
Summary:
Because llvm-dsymutil is using ASMPrinter without any MachineFunction
of Module available.

This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11078

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242384 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 05:59:25 +00:00
Adam Nemet
45646075c3 [LAA] Split out a helper to check the pointer partitions, NFC
This is made a static public member function to allow the transition of
this logic from LAA to LoopDistribution.  (Technically, it could be an
implementation-local static function but then it would not be accessible
from LoopDistribution.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242376 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 02:48:05 +00:00
Reid Kleckner
3cd5b05b14 Revert "[X86] Allow more call sequences to use push instructions for argument passing"
It miscompiles some code and a reduced test case has been sent to the
author.

This reverts commit r240257.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242373 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 01:30:00 +00:00
Reid Kleckner
7c898facbc Revert "Update LLVM bindings after r239940. ..."
Revert the changes to the C API LLVMBuildLandingPad that were part of
the personality function move. We now set the personality on the parent
function when the C API attempts to construct a landingpad with a
personality.

This reverts commit r240010.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242372 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 01:16:39 +00:00
Alex Lorenz
f7a602587e Fix broken testcase from r242358.
The testcase failed on non X86 targets, because I forgot to pass the
'-march=x86-64' option into llc for one of the X86 specific tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242370 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 00:58:33 +00:00
Akira Hatanaka
6780493e8d [ARM] Define a subtarget feature that is used to avoid using movt/movw
pairs for 32-bit immediates.

This change is needed to avoid emitting movt/movw pairs when doing LTO
and do so on a per-function basis.

Out-of-tree projects currently using cl::opt option -arm-use-movt=0 or
false to avoid emitting movt/movw pairs should make changes to add
subtarget feature "+no-movt" (see the changes made to clang in r242368).

rdar://problem/21529937

Differential Revision: http://reviews.llvm.org/D11026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242369 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 00:58:23 +00:00
Rafael Espindola
2cf6eb4a42 Trying to fix the windows bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242367 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 00:38:34 +00:00
Rafael Espindola
6a37b479b3 Fix handling of relative paths in thin archives.
The member has to end up with a path relative to the archive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242362 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 00:14:49 +00:00
Pete Cooper
076d176640 Clear kill flags in ARMLoadStoreOptimizer.
The pass here was clearing kill flags on instructions which had
their sources killed in the instruction being combined.  But
given that the new instruction is inserted after the existing ones,
any existing instructions with kill flags will lead to the verifier
complaining that we are reading an undefined physreg.

For example, what we had prior to this optimization is
	t2STRi12 %R1, %SP, 12
	t2STRi12 %R1<kill>, %SP, 16
	t2STRi12 %R0<kill>, %SP, 8

and prior to this fix that would generate
	t2STRi12 %R1<kill>, %SP, 16
	t2STRDi8 %R0<kill>, %R1, %SP, 8

This is clearly incorrect as it didn't clear the kill flag on R1
used with offset 16 because there was no kill flag on the instruction
with offset 12.

After this change we clear the kill flag on the offset 16 instruction
because we know it will be used afterwards in the new instruction.

I haven't provided a test case.  I have a small test, but even it is
very sensitive to register allocation order which isn't ideal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242359 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 00:09:18 +00:00
Alex Lorenz
a2e819fb09 MIR Serialization: Serialize the jump table index operands.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242358 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 23:38:35 +00:00
Alex Lorenz
81bef8c7a7 MIR Serialization: Serialize the jump table info.
The jump table info is serialized using a YAML mapping that contains its kind
and a YAML sequence of jump table entries. A jump table entry is a YAML mapping
that has an ID and an inline YAML sequence of machine basic block references.

The testcase 'CodeGen/MIR/X86/jump-table-info.mir' doesn't have any instructions
because one of them contains a jump table index operand. The jump table index
operands will be serialized in a follow up patch, and the appropriate
instructions will be added to this testcase.

Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242357 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 23:31:07 +00:00
Sean Silva
155c5e75fb Add a test for r242281 from an old patch of mine.
This isn't thorough, but should serve as a sanity check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242356 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 23:23:02 +00:00
Cong Hou
102d0382d4 Remove a private member of BranchProbabilityInfo which is not used at all.
The member to be removed is LoopInfo *LI.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242355 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 23:20:34 +00:00
Rafael Espindola
167af8c16c llvm-ar: Don't write the directory in the string table.
We were already doing the right thing for short file names, but not long
ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242354 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 23:15:33 +00:00
Cong Hou
8770f7af5f Create a wrapper pass for BranchProbabilityInfo.
This new wrapper pass is useful when we want to do branch probability analysis conditionally (e.g. only in PGO mode) but don't want to add one more pass dependence.

http://reviews.llvm.org/D11241



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242349 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 22:48:29 +00:00
David Majnemer
1ae7a81d26 Silence GCC -Wparenthesis warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242348 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 22:48:26 +00:00
Rafael Espindola
ba7661d294 For new archive member we only need to store the full path.
We were storing both the path and the file name, which was redundant
and easy to get confused up with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242347 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 22:46:53 +00:00
Chen Li
c2fa6d64b4 [LoopUnswitch] Add an else clause to IsTrivialUnswitchCondition() when checking HeaderTerm instruction type
Summary:
This is a trivial code change with no functionality effect. 

When LoopUnswitch determines trivial unswitch condition, it checks whether the loop header's terminator instruction is a branch instruction or switch instruction since trivial unswitch condition can only apply to these two instruction types. The current code does not fail the check directly on other instruction types, but check the nullness of LoopExitBB variable instead. The added else clause makes the check fail immediately on other instruction types and makes the code more obvious.  

Reviewers: reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11239

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242345 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 22:41:13 +00:00
Hans Wennborg
db210912ad test-release.sh: Run both .o files through sed before comparing them
On some systems (e.g. Mac OS X), sed will add a newline to the end of
the output if there wasn't one already. This would cause false
cmp errors since the .o file from Phase 2 was passed through sed and
the one from Phase 3 wasn't. Work around this by passing both through
sed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242341 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 22:18:25 +00:00
Matthias Braun
2aa5727755 TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints()
Pass a const reference to LiveRegMatrix to getRegAllocationHints()
because some targets can prodive better hints if they can test whether a
physreg has been used for register allocation yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242340 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 22:16:00 +00:00
Alex Lorenz
71da3635d9 MIR Serialization: Serialize references from the stack objects to named allocas.
This commit serializes the references to the named LLVM alloca instructions from
the stack objects in the machine frame info. This commit adds a field 'Name' to
the struct 'yaml::MachineStackObject'. This new field is used to store the name
of the alloca instruction when the alloca is present and when it has a name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242339 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 22:14:49 +00:00
Paul Robinson
641735d426 Add a "debugger tuning" concept that allows us to fine-tune how we
emit debug info, according to the preferences of the different
debuggers used on various targets.
Darwin and FreeBSD default to tuning for LLDB; PS4 defaults to tuning for
the SCE (Sony Computer Entertainment) debugger.  All others default to GDB.

Differential Revision: http://reviews.llvm.org/D8506


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242338 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 22:04:54 +00:00
JF Bastien
063eb4e389 Fix mergefunc infinite loop
Self-referential constants containing references to a merged function
no longer cause the MergeFunctions pass to infinite loop. Also adds a
reproduction IR which would otherwise fail, which was isolated from a similar
issue in Chromium.

Author: jrkoenig
Reviewers: nlewycky, jfb
Subscribers: llvm-commits, nlewycky, jfb

Differential Revision: http://reviews.llvm.org/D11208

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242337 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 21:51:33 +00:00
Rafael Espindola
a0458b67ae Simplify a few uses of remove_filename by using parent_path instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242334 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 21:24:07 +00:00
Hans Wennborg
f9893938de Switch the release script to build with CMake by default (PR21561)
It retains the possibility to use the autoconf build with a
command-line option ('-use-autoconf'), and uses that by default on Darwin since
compiler-rt requires it on that platform.

This commit also removes the "Release-64" flavour and related logic. The script
would previously do two builds unless the '-no-64bit' flag was passed, but on
my machine and from those I asked this always ended up producing two 64-bit builds,
causing much confusion.

It also removes the -build-triple option, which caused the --build= flag to
get passed to ./configure. This was presumably intended for cross-compiling,
but none of the release testers use it. If someone does want to pass it,
they can use '-configure-flags --build=foo' instead.

Differential Revision: http://reviews.llvm.org/D10715

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242331 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 21:06:16 +00:00
Rafael Espindola
8d1daf644b Handle the error of trying to convert a regular archive to a thin one.
While at it, test that we can add to a thin archive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242330 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 20:45:56 +00:00
Cong Hou
2fa118d257 Rename doFunction() in BFI to calculate() and change its parameters from pointers to references.
http://reviews.llvm.org/D11196



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242322 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 19:58:26 +00:00
Tobias Edler von Koch
3659b8adc9 Analyze recursive PHI nodes in BasicAA
Summary:
This patch allows phi nodes like
  %x = phi [ %incptr, ... ] [ %var, ... ]
  %incptr = getelementptr %x, 1
to be analyzed by BasicAliasAnalysis.

In aliasPHI, we can detect incoming values that are recursive GEPs with a
constant offset. Instead of trying to analyze a recursive GEP (and failing), 
we now ignore it and instead set the size of the memory referenced by
the PHINode to UnknownSize. This represents all the possible memory
locations the pointer represented by the PHINode could be advanced to
by the GEP.

For now, this new behavior is turned off by default to allow debugging of
performance degradations seen with SPEC/x86 and Hexagon benchmarks.
The flag -basicaa-recphi turns it on.


Reviewers: hfinkel, sanjoy

Subscribers: tobiasvk_caf, sanjoy, llvm-commits

Differential Revision: http://reviews.llvm.org/D10368

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242320 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 19:32:22 +00:00
Bruno Cardoso Lopes
162c547bf6 Revert "Refactor optimizeUncoalescable logic"
Likely broke compilation on ARM:

http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/13054

This reverts commit 0b7824464fbe3d3f386e2d4aef6a431422709e53.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242311 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 18:10:46 +00:00
Bruno Cardoso Lopes
ae1ebf6cf7 Revert "Look through PHIs to find additional register sources"
Likely broke compilation on ARM:

http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/13054

This reverts commit 131ce4a838c081516cbfed039fc986b33e3979d6.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242310 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 18:10:35 +00:00
Cong Hou
15afc3140e Test commit.
This is a test commit (one blank line deleted).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242308 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 17:58:15 +00:00
Rafael Espindola
b7faac8a2e Delete declared but not implemented functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242304 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 17:19:39 +00:00
Adrian Prantl
bd584159e1 Debug Info: Add basic support for external types references.
This is a necessary prerequisite for bootstrapping the emission
of debug info inside modules.

- Adds a FlagExternalTypeRef to DICompositeType.
  External types must have a unique identifier.
- External type references are emitted using a forward declaration
  with a DW_AT_signature([DW_FORM_ref_sig8]) based on the UID.

http://reviews.llvm.org/D9612

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242302 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 17:01:41 +00:00
Pete Cooper
745b733071 Add missing load/store flags to thumb2 instructions.
These were the cause of a verifier error when building 7zip with
-verify-machineinstrs.  Running 'make check' with the verifier
triggered the same error on the test here so i've updated the test
to run the verifier on one of its runs instead of adding a new one.

While looking at this code, there was a stale comment that these
instructions were only used for disassembly.  This probably used to
be the case, but they are now used in the 'ARM load / store optimization pass' too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242300 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 16:36:38 +00:00
Bill Schmidt
aa2200c5fa [PPC64LE] Fix vec_sld semantics for little endian
The vec_sld interface provides access to the vsldoi instruction.
Unlike most of the vec_* interfaces, we do not attempt to change the
generated code for vec_sld based on the endian mode.  It is too
difficult to correctly infer the desired semantics because of
different element types, and the corrected instruction sequence is
expensive, involving loading a permute control vector and performing a
generalized permute.

For GCC, this was implemented as "Don't touch the vec_sld"
implementation.  When it came time for the LLVM implementation, I did
the same thing.  However, this was hasty and incorrect.  In LLVM's
version of altivec.h, vec_sld was previously defined in terms of the
vec_perm interface.  Because vec_perm semantics are adjusted for
little endian, this means that leaving vec_sld untouched causes it to
generate something different for LE than for BE.  Not good.

This back-end patch accompanies the changes to altivec.h that change
vec_sld's behavior for little endian.  Those changes mean that we see
slightly different code in the back end when trying to recognize a
VSLDOI instruction in isVSLDOIShuffleMask.  In particular, a
ShuffleKind of 1 (where the two inputs are identical) must now be
treated the same way as a ShuffleKind of 2 (little endian with
different inputs) when little endian mode is in force.  This is
because ShuffleKind of 1 is defined using big-endian numbering.

This has a ripple effect on LowerBUILD_VECTOR, where we create our own
internal VSLDOI instructions.  Because these are a ShuffleKind of 1,
they will now have their shift amounts subtracted from 16 when
recognizing the shuffle mask.  To avoid problems we have to subtract
them from 16 again before creating the VSLDOI instructions.

There are a couple of other uses of BuildVSLDOI, but these do not need
to be modified because the shift amount is 8, which is unchanged when
subtracted from 16.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242296 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 15:45:30 +00:00
Bruno Cardoso Lopes
b11d8102cf Look through PHIs to find additional register sources
- Teaches the ValueTracker in the PeepholeOptimizer to look through PHI
instructions.
- Add findNextSourceAndRewritePHI method to lookup into multiple sources
returnted by the ValueTracker and rewrite PHIs with new sources.

With these changes we can find more register sources and rewrite more
copies to allow coaslescing of bitcast instructions. Hence, we eliminate
unnecessary VR64 <-> GR64 copies in x86, but it could be extended to
other archs by marking "isBitcast" on target specific instructions. The
x86 example follows:

A:
  psllq %mm1, %mm0
  movd  %mm0, %r9
  jmp C

B:
  por %mm1, %mm0
  movd  %mm0, %r9
  jmp C

C:
  movd  %r9, %mm0
  pshufw  $238, %mm0, %mm0

Becomes:

A:
  psllq %mm1, %mm0
  jmp C

B:
  por %mm1, %mm0
  jmp C

C:
  pshufw  $238, %mm0, %mm0

Differential Revision: http://reviews.llvm.org/D11197

rdar://problem/20404526

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242295 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 15:35:23 +00:00
Bruno Cardoso Lopes
7c72a2254c Refactor optimizeUncoalescable logic
- Create a new CopyRewriter for Uncoalescable copy-like instructions
- Change the ValueTracker to return a ValueTrackerResult

This makes optimizeUncoalescable looks more like optimizeCoalescable and
use the CopyRewritter infrastructure.

This is also the preparation for looking up into PHI nodes in the
ValueTracker.

Differential Revision: http://reviews.llvm.org/D11195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242294 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 15:35:09 +00:00
Andrew Wilkins
9226c071b0 Expose setPersonalityFn to Go
Summary:
Add Value.SetPersonality to the Go bindings. The Go
bindings' Builder.CreateLandingPad has been updated,
removing the obsolete personality argument.

Background

The personality attribute was removed from LandingPadInst
in r239940, and llvm::Function::setPersonalityFn introduced.

There was no corresponding change to either the C API or
Go bindings. The Go bindings were broken until r239940, but
that change was just to ignore the personality argument.
This broke llgo.

Reviewers: majnemer, pcc

Subscribers: deadalnix, llvm-commits, axw

Differential Revision: http://reviews.llvm.org/D11116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242289 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 13:03:08 +00:00
Benjamin Kramer
17351cfb43 [PPC] Disassemble little endian ppc instructions in the right byte order
PR24122. The test is simply a byte swapped version of ppc64-encoding.txt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242288 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 12:56:19 +00:00
Alexandros Lamprineas
4aa2f4514c -Added API for retrieving the default FPU of a CPU from TargetParser.
-Implemented as a table lookup.

Change-Id: Iaad0eaf4b29b06827e6700269496dc1ba20e9018
Phabricator: http://reviews.llvm.org/D11100

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242284 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 10:46:21 +00:00
Chandler Carruth
7d51923226 [PM/AA] Fix *numerous* serious bugs in GlobalsModRef found by
inspection.

While we want to handle calls specially in this code because they should
have been modeled by the call graph analysis that precedes it, we should
*not* be re-implementing the predicates for whether an instruction reads
or writes memory. Those are well defined already. Notably, at least the
following issues seem to be clearly missed before:
- Ordered atomic loads can "write" to memory by causing writes from other
  threads to become visible. Similarly for ordered atomic stores.
- AtomicRMW instructions quite obviously both read and write to memory.
- AtomicCmpXchg instructions also read and write to memory.
- Fences read and write to memory.
- Invokes of intrinsics or memory allocation functions.

I don't have any test cases, and I suspect this has never really come up
in the real world. But there is no reason why it wouldn't, and it makes
the code simpler to do this the right way.

While here, I've tried to make the loops significantly simpler as well
and added helpful comments as to what is going on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242281 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 08:53:29 +00:00
Alexey Bataev
a018099669 [SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)
Current implementation handles unordered comparison poorly in soft-float mode. 
Consider (a ULE b) which is a <= b. It is lowered to (ledf2(a, b) <= 0 || unorddf2(a, b) != 0) (in general). We can do better job by lowering it to (__gtdf2(a, b) <= 0). 
Such replacement is true for other CMP's (ult, ugt, uge). In general, we just call same function as for ordered case but negate comparison against zero.
Differential Revision: http://reviews.llvm.org/D10804


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242280 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 08:39:35 +00:00
Hal Finkel
8913d18fb1 [PowerPC] Use the MachineCombiner to reassociate fadd/fmul
This is a direct port of the code from the X86 backend (r239486/r240361), which
uses the MachineCombiner to reassociate (floating-point) adds/muls to increase
ILP, to the PowerPC backend. The rationale is the same.

There is a lot of copy-and-paste here between the X86 code and the PowerPC
code, and we should extract at least some of this into CodeGen somewhere.
However, I don't want to do that until this code is enhanced to handle FMAs as
well. After that, we'll be in a better position to extract the common parts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242279 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 08:23:05 +00:00
Hal Finkel
e4edd6cd8e [PowerPC] Extend physical register live range in PPCVSXFMAMutate
If the source of the copy that defines the addend is a physical register, then
its existing live range may not extend to the FMA being mutated. Make sure we
extend the live range of the register to meet the FMA because it will become
its operand in this case.

I don't have an independent test case, but it will be exposed by change to be
committed shortly enabling the use of the machine combiner to do fadd/fmul
reassociation, and will be covered by one of the associated regression tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242278 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 08:23:03 +00:00
Hal Finkel
b2a353c753 [MachineCombiner] Work with itineraries
MachineCombiner predicated its use of scheduling-based metrics on
hasInstrSchedModel(), but useful conclusions can be drawn from pipeline
itineraries as well. Almost all of the logic (except for resource tracking in
preservesResourceLen) can be used if we have an itinerary, so enable it in that
case as well.

This will be used by the PowerPC backend in an upcoming commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242277 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 08:22:23 +00:00
Petr Pavlu
ec223f1217 [AArch64] Fix problems in decoding generic MSR instructions
Bitpatterns rejected by the decoder method of `MSR (immediate)` should be
decoded as the `extended MSR (register)` instruction.

Differential Revision: http://reviews.llvm.org/D7174


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242276 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 08:10:30 +00:00
Chandler Carruth
f31b1ec106 [PM/AA] Cleanup some loops to be range-based. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242275 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 08:09:23 +00:00
Petr Pavlu
d2e1e42c1a [TableGen] Improve decoding options for non-orthogonal instructions
When FixedLenDecoder matches an input bitpattern of form [01]+ with an
instruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are
mixed/variable bits) it passes the input bitpattern to a specific instruction
decoder method which then makes a final decision whether the bitpattern is a
valid instruction or not. This means the decoder must handle all possible
values of the variable bits which sometimes leads to opcode rewrites in the
decoder method when the instructions are not fully orthogonal.

The patch provides a way for the decoder method to say that when it returns
Fail it does not necessarily mean the bitpattern is invalid, but rather that
the bitpattern is definitely not an instruction that is recognized by the
decoder method. The decoder can then try to match the input bitpattern with
other possible instruction bitpatterns.

For example, this allows to solve a situation on AArch64 where the `MSR
(immediate)` instruction has form:
1101 0101 0000 0??? 0100 ???? ???1 1111
but not all values of the ? bits are allowed. The rejected values should be
handled by the `extended MSR (register)` instruction:
1101 0101 000? ???? ???? ???? ???? ????

The decoder will first try to decode an input bitpattern that matches both
bitpatterns as `MSR (immediate)` but currently this puts the decoder method of
`MSR (immediate)` into a situation when it must be able to decode all possible
values of the ? bits, i.e. it would need to rewrite the instruction to `MSR
(register)` when it is not `MSR (immediate)`.

The patch allows to specify that the decoder method cannot determine if the
instruction is valid for all variable values. The decoder method can simply
return Fail when it knows it is definitely not `MSR (immediate)`. The decoder
will then backtrack the decoding and find that it can match the input
bitpattern with the more generic `MSR (register)` bitpattern too.

Differential Revision: http://reviews.llvm.org/D7174


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242274 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 08:04:27 +00:00
Simon Pilgrim
ccadf0b1b4 [X86][SSE] Added i686/SSE2 vector shift tests.
We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242273 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 08:04:07 +00:00