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5983 Commits

Author SHA1 Message Date
Stephen Lin
7e6d620336 SelectionDAG: slightly refactor DAGCombiner::visitSELECT_CC to avoid redudant checks... 
This doesn't really effect performance due to all the relevant calls being transparent but is clearer. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184027 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-15 04:03:33 +00:00
Matt Arsenault
b05e4778f0 Introduce getSelect usage and use more getSelectCC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184012 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:04:37 +00:00
Stephen Lin
a553bede23 SelectionDAG: minor fix to order of operands in comments to match the code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184008 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 21:33:58 +00:00
Stephen Lin
38103d1012 SelectionDAG: Fix incorrect condition checks in some cases of folding FADD/FMUL combinations; also improve accuracy of comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183993 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 18:17:35 +00:00
David Majnemer
a2f8d37fb7 TargetLowering: Clean up method description comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183623 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-08 23:51:45 +00:00
Bill Wendling
6a2e7ac0b6 Cache the TargetLowering info object as a pointer. 
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 00:43:09 +00:00
Bill Wendling
384ceb8446 Don't cache the TargetLoweringInfo object inside of the FunctionLowering object. 
The TargetLoweringInfo object is owned by the TargetMachine. In the future, the
TargetMachine object may change, which may also change the TargetLoweringInfo
object.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183356 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 00:11:39 +00:00
Andrew Trick
6e0b2a0cb0 Order CALLSEQ_START and CALLSEQ_END nodes. 
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-29 22:03:55 +00:00
Benjamin Kramer
520b6e3fa5 Simplify code. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182779 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-28 16:39:36 +00:00
Benjamin Kramer
e4fae84b0b Remove double semicolons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182778 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-28 16:31:26 +00:00
Preston Gurd
b704d23062 Convert sqrt functions into sqrt instructions when -ffast-math is in effect. 
When -ffast-math is in effect (on Linux, at least), clang defines
__FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the
preprocessor to include <bits/math-finite.h>, which renames the sqrt functions.
For instance, "sqrt" is renamed as "__sqrt_finite". 

This patch adds the 3 new names in such a way that they will be treated
as equivalent to their respective original names.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182739 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-27 15:44:35 +00:00
Andrew Trick
9edb37feb5 Fix PR16143: Insert DEBUG_VALUE before terminator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182717 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-26 08:58:50 +00:00
Andrew Trick
dd0fb018a7 Track IR ordering of SelectionDAG nodes 3/4. 
Remove the old IR ordering mechanism and switch to new one.  Fix unit
test failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182704 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-25 03:08:10 +00:00
Andrew Trick
ac6d9bec67 Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-25 02:42:55 +00:00
Andrew Trick
ea5db0c315 Track IR ordering of SelectionDAG nodes 1/4. 
Use a field in the SelectionDAGNode object to track its IR ordering.
This adds fields and utility classes without changing existing
interfaces or functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182701 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-25 02:20:36 +00:00
Michael J. Spencer
c6af2432c8 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-24 22:23:49 +00:00
Adrian Prantl
5da4e4f3b1 Unify formatting of debug output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182495 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-22 18:02:19 +00:00
Justin Holewinski
c2b7f5fa51 Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen. 
The intrinsic calls are dropped, but the annotated value is propagated.

Fixes PR 15253

Original patch by Zeng Bin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182387 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-21 14:37:16 +00:00
Benjamin Kramer
f19b8b018b DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0. 
Fixes PR16083.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182357 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-21 08:51:09 +00:00
Matt Arsenault
225ed7069c Add LLVMContext argument to getSetCCResultType 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-18 00:21:46 +00:00
Matt Arsenault
9aa8fdfddb Replace redundant code 
Use EVT::changeExtendedVectorElementTypeToInteger instead of doing the
same thing that it does

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182165 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 21:43:43 +00:00
Matt Arsenault
63f3ca5da7 Add missing -*- C++ -*- to headers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182164 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 21:43:39 +00:00
Adrian Prantl
df68803890 Generate debug info for by-value struct args even if they are not used. 
radar://problem/13865940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182062 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-16 23:44:12 +00:00
Benjamin Kramer
8401ed21aa DAGCombine: Also shrink eq compares where the constant is exactly as large as the smaller type. 
if ((x & 255) == 255)

before: movzbl  %al, %eax
        cmpl  $255, %eax

after:  cmpb  $-1, %al

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182038 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-16 18:47:58 +00:00
Hal Finkel
71da6755c8 Fix legalization of SETCC with promoted integer intrinsics 
If the input operands to SETCC are promoted, we need to make sure that we
either use the promoted form of both operands (or neither); a mixture is not
allowed. This can happen, for example, if a target has a custom promoted
i1-returning intrinsic (where i1 is not a legal type). In this case, we need to
use the promoted form of both operands.

This change only augments the behavior of the existing logic in the case where
the input types (which may or may not have already been legalized) disagree,
and should not affect existing target code because this case would otherwise
cause an assert in the SETCC operand promotion code.

This will be covered by (essentially all of the) tests for the new PPCCTRLoops
infrastructure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181926 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-15 21:37:27 +00:00
Bob Wilson
a753ff72b2 Remove redundant variable introduced by r181682. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181721 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-13 19:02:31 +00:00
Hao Liu
3778c04b2e Fix PR15950 A bug in DAG Combiner about undef mask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181682 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-13 02:07:05 +00:00
Benjamin Kramer
768ebcdf63 DAGCombiner: Generate a correct constant for vector types when folding (xor (and)) into (and (not)). 
PR15948.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181597 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 14:09:52 +00:00
Owen Anderson
58dcd200b7 Teach SelectionDAG to constant fold all-constant FMA nodes the same way that it constant folds FADD, FMUL, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181555 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-09 22:27:13 +00:00
David Majnemer
363160a6be DAGCombiner: Simplify inverted bit tests 
Fold (xor (and x, y), y) -> (and (not x), y)

This removes an opportunity for a constant to appear twice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181395 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-08 06:44:42 +00:00
Matt Arsenault
798925bac7 Fix vselect when getSetCCResultType returns a different type from the operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181348 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 20:24:18 +00:00
Michael Kuperstein
2720248ae5 Fix slightly too aggressive conact_vector optimization. 
(Would sometimes optimize away conacts used to extend a vector with undef values)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181186 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 08:06:13 +00:00
Dmitri Gribenko
5c332dbd30 Add ArrayRef constructor from None, and do the cleanups that this constructor enables 
Patch by Robert Wilhelm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181138 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-05 00:40:33 +00:00
Chad Rosier
f0b0755b6e [inline asm] Return an undef SDValue of the expected value type, rather than 
report a fatal error.  This allows us to continue processing the translation
unit.  Test case to come on the clang side because we need an inline asm
diagnostics handler in place.
rdar://13446483

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180873 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-01 19:49:26 +00:00
Nadav Rotem
b2ed5fac06 Optimize away nop CONCAT_VECTOR nodes. 
Optimize CONCAT_VECTOR nodes that merge EXTRACT_SUBVECTOR values that extract from the same vector.

rdar://13402653
PR15866



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180871 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-01 19:18:51 +00:00
Stephen Lin
3484da9479 Only pass 'returned' to target-specific lowering code when the value of entire register is guaranteed to be preserved. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180825 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 22:49:28 +00:00
Adrian Prantl
86a87d9ba1 Temporarily revert "Change the informal convention of DBG_VALUE so that we can express a" 
because it breaks some buildbots.

This reverts commit 180816.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180819 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 22:35:14 +00:00
Adrian Prantl
a2b56692c8 Change the informal convention of DBG_VALUE so that we can express a 
register-indirect address with an offset of 0.
It used to be that a DBG_VALUE is a register-indirect value if the offset
(operand 1) is nonzero. The new convention is that a DBG_VALUE is
register-indirect if the first operand is a register and the second
operand is an immediate. For plain registers use the combination reg, reg.

rdar://problem/13658587

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180816 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 22:16:46 +00:00
Silviu Baranga
730a570c8c Re-write the address propagation code for pre-indexed loads/stores to take into account some previously misssed cases (PRE_DEC addressing mode, the offset and base address are swapped, etc). This should fix PR15581. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180609 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-26 15:52:24 +00:00
Benjamin Kramer
6242fda42a DAGCombiner: Canonicalize vector integer abs in the same way we do it for scalars. 
This already helps SSE2 x86 a lot because it lacks an efficient way to
represent a vector select. The long term goal is to enable the backend to match
a canonicalized pattern into a single instruction (e.g. vabs or pabs).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180597 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-26 09:19:19 +00:00
Silviu Baranga
02066838b5 Fix constant folding for one lane vector types. Constant folding one lane vector types not returns a vector instead of a scalar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180254 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-25 09:32:33 +00:00
Chad Rosier
2871ba90a3 [inline asm] Fix a crasher for an invalid value type/register class. 
rdar://13731657


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180226 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-24 22:53:10 +00:00
Owen Anderson
ed5707baf9 DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider VSETCC without first checking the target's vector boolean contents. 
This exposed an issue with PowerPC AltiVec where it appears it was setting the wrong vector boolean contents.  The included change
fixes the PowerPC tests, and was OK'd by Hal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180129 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 18:09:28 +00:00
Jim Grosbach
0cb1019e9c Legalize vector truncates by parts rather than just splitting. 
Rather than just splitting the input type and hoping for the best, apply
a bit more cleverness. Just splitting the types until the source is
legal often leads to an illegal result time, which is then widened and a
scalarization step is introduced which leads to truly horrible code
generation. With the loop vectorizer, these sorts of operations are much
more common, and so it's worth extra effort to do them well.

Add a legalization hook for the operands of a TRUNCATE node, which will
be encountered after the result type has been legalized, but if the
operand type is still illegal. If simple splitting of both types
ends up with the result type of each half still being legal, just
do that (v16i16 -> v16i8 on ARM, for example). If, however, that would
result in an illegal result type (v8i32 -> v8i8 on ARM, for example),
we can get more clever with power-two vectors. Specifically,
split the input type, but also widen the result element size, then
concatenate the halves and truncate again.  For example on ARM,
To perform a "%res = v8i8 trunc v8i32 %in" we transform to:
  %inlo = v4i32 extract_subvector %in, 0
  %inhi = v4i32 extract_subvector %in, 4
  %lo16 = v4i16 trunc v4i32 %inlo
  %hi16 = v4i16 trunc v4i32 %inhi
  %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
  %res = v8i8 trunc v8i16 %in16

This allows instruction selection to generate three VMOVN instructions
instead of a sequences of moves, stores and loads.

Update the ARMTargetTransformInfo to take this improved legalization
into account.

Consider the simplified IR:

define <16 x i8> @test1(<16 x i32>* %ap) {
  %a = load <16 x i32>* %ap
  %tmp = trunc <16 x i32> %a to <16 x i8>
  ret <16 x i8> %tmp
}

define <8 x i8> @test2(<8 x i32>* %ap) {
  %a = load <8 x i32>* %ap
  %tmp = trunc <8 x i32> %a to <8 x i8>
  ret <8 x i8> %tmp
}

Previously, we would generate the truly hideous:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #20
	bic	sp, sp, #7
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d24, d25}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	vld1.64	{d18, d19}, [r2:128]
	add	r1, r0, #16
	vmovn.i32	d22, q8
	vld1.64	{d16, d17}, [r1:128]
	vmovn.i32	d20, q9
	vmovn.i32	d18, q12
	vmov.u16	r0, d22[3]
	strb	r0, [sp, #15]
	vmov.u16	r0, d22[2]
	strb	r0, [sp, #14]
	vmov.u16	r0, d22[1]
	strb	r0, [sp, #13]
	vmov.u16	r0, d22[0]
	vmovn.i32	d16, q8
	strb	r0, [sp, #12]
	vmov.u16	r0, d20[3]
	strb	r0, [sp, #11]
	vmov.u16	r0, d20[2]
	strb	r0, [sp, #10]
	vmov.u16	r0, d20[1]
	strb	r0, [sp, #9]
	vmov.u16	r0, d20[0]
	strb	r0, [sp, #8]
	vmov.u16	r0, d18[3]
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	vldmia	sp, {d16, d17}
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	mov	sp, r7
	pop	{r7}
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #12
	bic	sp, sp, #7
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d20, d21}, [r0:128]
	vmovn.i32	d18, q8
	vmov.u16	r0, d18[3]
	vmovn.i32	d16, q10
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	ldm	sp, {r0, r1}
	mov	sp, r7
	pop	{r7}
	bx	lr

Now, however, we generate the much more straightforward:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d20, d21}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	add	r1, r0, #16
	vld1.64	{d18, d19}, [r2:128]
	vld1.64	{d22, d23}, [r1:128]
	vmovn.i32	d17, q8
	vmovn.i32	d16, q9
	vmovn.i32	d18, q10
	vmovn.i32	d19, q11
	vmovn.i16	d17, q8
	vmovn.i16	d16, q9
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d18, d19}, [r0:128]
	vmovn.i32	d16, q8
	vmovn.i32	d17, q9
	vmovn.i16	d16, q8
	vmov	r0, r1, d16
	bx	lr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179989 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-21 23:47:41 +00:00
Jim Grosbach
1e48093df8 Tidy up comment grammar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179986 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-21 21:23:01 +00:00
Tim Northover
6265d5c91a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 12:32:17 +00:00
Stephen Lin
456ca048af Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179925 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 05:14:40 +00:00
Eli Bendersky
462123f661 Simplify the code in FastISel::tryToFoldLoad, add an assertion and fix a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179908 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 23:26:18 +00:00
Eli Bendersky
75299e3a95 Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'm 
trying to move as much FastISel logic as possible out of the main path in
SelectionDAGISel - intermixing them just adds confusion.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179902 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 22:29:18 +00:00
Michael Liao
2a8bea7a8e ArrayRefize getMachineNode(). No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 22:22:57 +00:00