Andrew Trick ea5db0c315 Track IR ordering of SelectionDAG nodes 1/4. ... Use a field in the SelectionDAGNode object to track its IR ordering. This adds fields and utility classes without changing existing interfaces or functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182701 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-25 02:20:36 +00:00
..
CMakeLists.txt	llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.	2012-06-24 13:32:01 +00:00
DAGCombiner.cpp	Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.	2013-05-24 22:23:49 +00:00
FastISel.cpp	Unify formatting of debug output.	2013-05-22 18:02:19 +00:00
FunctionLoweringInfo.cpp	Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects.	2013-02-08 20:35:15 +00:00
InstrEmitter.cpp	Temporarily revert "Change the informal convention of DBG_VALUE so that we can express a"	2013-04-30 22:35:14 +00:00
InstrEmitter.h	Use MachineInstrBuilder in InstrEmitter.	2012-12-20 18:08:09 +00:00
LegalizeDAG.cpp	Add LLVMContext argument to getSetCCResultType	2013-05-18 00:21:46 +00:00
LegalizeFloatTypes.cpp	Add LLVMContext argument to getSetCCResultType	2013-05-18 00:21:46 +00:00
LegalizeIntegerTypes.cpp	Add LLVMContext argument to getSetCCResultType	2013-05-18 00:21:46 +00:00
LegalizeTypes.cpp	Move SDNode order propagation to SDNodeOrdering, which also fixes a missed	2013-03-20 14:51:01 +00:00
LegalizeTypes.h	Add LLVMContext argument to getSetCCResultType	2013-05-18 00:21:46 +00:00
LegalizeTypesGeneric.cpp	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
LegalizeVectorOps.cpp	Add LLVMContext argument to getSetCCResultType	2013-05-18 00:21:46 +00:00
LegalizeVectorTypes.cpp	Add LLVMContext argument to getSetCCResultType	2013-05-18 00:21:46 +00:00
LLVMBuild.txt	LLVMBuild: Remove trailing newline, which irked me.	2011-12-12 19:48:00 +00:00
Makefile
ResourcePriorityQueue.cpp	Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.	2012-12-13 06:34:11 +00:00
ScheduleDAGFast.cpp	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
ScheduleDAGRRList.cpp	Revert "pre-RA-sched: fix TargetOpcode usage"	2013-03-20 15:43:00 +00:00
ScheduleDAGSDNodes.cpp	Change TargetLowering::getRepRegClassFor to take an MVT, instead of	2012-12-13 18:45:35 +00:00
ScheduleDAGSDNodes.h	Fix #includes, so we include only what we really need.	2013-02-20 00:26:25 +00:00
ScheduleDAGVLIW.cpp	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
SDNodeDbgValue.h	Sort includes for all of the .h files under the 'lib' tree. These were	2012-12-04 07:12:27 +00:00
SDNodeOrdering.h	Make variable name more explicit and eliminate redundant lookup in SDNodeOrdering	2013-03-20 23:10:59 +00:00
SelectionDAG.cpp	Teach SelectionDAG to constant fold all-constant FMA nodes the same way that it constant folds FADD, FMUL, etc.	2013-05-09 22:27:13 +00:00
SelectionDAGBuilder.cpp	Track IR ordering of SelectionDAG nodes 1/4.	2013-05-25 02:20:36 +00:00
SelectionDAGBuilder.h	Track IR ordering of SelectionDAG nodes 1/4.	2013-05-25 02:20:36 +00:00
SelectionDAGDumper.cpp	Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.	2013-04-20 12:32:17 +00:00
SelectionDAGISel.cpp	Temporarily revert "Change the informal convention of DBG_VALUE so that we can express a"	2013-04-30 22:35:14 +00:00
SelectionDAGPrinter.cpp	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
TargetLowering.cpp	DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0.	2013-05-21 08:51:09 +00:00
TargetSelectionDAGInfo.cpp	Move TargetData to DataLayout.	2012-10-08 16:38:25 +00:00