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21165 Commits

Author SHA1 Message Date
Daniel Sanders
a6e253ddd0 [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192438 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:50:42 +00:00
Daniel Sanders
4fa2c32220 [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:27:32 +00:00
Robert Lytton
ed0ed946ab XCore target fix bug in emitArrayBound() causing segmentation fault 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192434 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:27:13 +00:00
Robert Lytton
4315b2b504 XCore target does not emit '.hidden' or '.protected' attributes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192433 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:27:00 +00:00
Robert Lytton
fb312f9f5a XCore target: fix bug in XCoreLowerThreadLocal.cpp 
When a ConstantExpr which uses a thread local is part of a PHI node
instruction, the insruction that replaces the ConstantExpr must
be inserted in the predecessor block, in front of the terminator instruction.
If the predecessor block has multiple successors, the edge is first split.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192432 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:26:48 +00:00
Robert Lytton
7b5376659c XCore target: add XCoreTargetLowering::isZExtFree() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192431 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:26:29 +00:00
Daniel Sanders
c879eabcc2 [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:14:25 +00:00
Daniel Sanders
b9bee10b21 [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:00:06 +00:00
Kevin Qin
767f816b92 Implement aarch64 neon instruction set AdvSIMD (copy). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 02:33:55 +00:00
Matthias Braun
b803d6bf62 Tests: Do not unnecessarily depend on kill comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192404 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 22:37:49 +00:00
Matthias Braun
82eb6198c8 Tests: Use CHECK-LABEL where possible 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192403 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 22:37:47 +00:00
Manman Ren
b8e48a636e Debug Info: In DIBuilder, the context field of subprogram is updated to use 
DIScopeRef.

A paired commit at clang is required due to changes to DIBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192378 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 18:40:01 +00:00
Manman Ren
75a3ad485c Add comments to debug info testing case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192376 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 18:13:17 +00:00
Matt Arsenault
1cc41bf63c R600: Fix trunc i64 to i32 on SI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192375 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 18:04:16 +00:00
Tom Stellard
3986785046 R600/SI: Use -verify-machineinstrs for most tests 
We can't enable the verifier for tests with SI_IF and SI_ELSE, because
these instructions are always followed by a COPY which copies their
result to the next basic block.  This violates the machine verifier's
rule that non-terminators can not folow terminators.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 17:11:46 +00:00
Hao Liu
6a5a667517 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 17:00:52 +00:00
Rafael Espindola
812ddcc50f Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." 
This reverts commit r192352. It broke the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 15:15:17 +00:00
Hao Liu
d622bef31d Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 15:01:24 +00:00
Benjamin Kramer
58e3e1021d Disable function padding to get this test to pass on atom. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192348 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 12:46:23 +00:00
Tim Northover
acd79ce0ad ARM: correct liveness flags during ARMLoadStoreOpt 
When we had a sequence like:

    s1 = VLDRS [r0, 1], Q0<imp-def>
    s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
    s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
    s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>

we were gathering the {s0, s1} loads below the s3 load. This is fine,
but confused the verifier since now the s3 load had Q0<imp-use> with
no definition above it.

This should mark such uses <undef> as well. The liveness structure at
the beginning and end of the block is unaffected, and the true sN
definitions should prevent any dodgy reorderings being introduced
elsewhere.

rdar://problem/15124449

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192344 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 09:28:20 +00:00
Craig Topper
15de63cfde Allow non-AVX form of pmovmskb to take a GR64 operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192341 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 05:33:31 +00:00
Akira Hatanaka
25dafa388a [mips] Do not generate INS/EXT nodes if target does not have support for 
ins/ext.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192330 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 23:36:17 +00:00
Manman Ren
b4d9c11f6c Debug Info: In DIBuilder, the context and type fields of template_type and 
template_value are updated to use DIRef.

A paired commit at clang is required due to changes to DIBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192320 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 19:46:28 +00:00
Manman Ren
5e5d494ce0 Debug Info: In DIBuilder, the context field of a forward decl is updated 
to use DIScopeRef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192309 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 18:10:55 +00:00
Shuxin Yang
e0409098ae Fix a bug in Dead Argument Elimination. 
If a function seen at compile time is not necessarily the one linked to
the binary being built, it is illegal to change the actual arguments
passing to it. 

  e.g. 
   --------------------------
   void foo(int lol) {
     // foo() has linkage satisifying isWeakForLinker()
     // "lol" is not used at all.
   }

   void bar(int lo2) {
      // xform to foo(undef) is illegal, as compiler dose not know which
      // instance of foo() will be linked to the the binary being built.
      foo(lol2); 
   }
  -----------------------------

  Such functions can be captured by isWeakForLinker(). NOTE that
mayBeOverridden() is insufficient for this purpose as it dosen't include
linkage types like AvailableExternallyLinkage and LinkOnceODRLinkage.
Take link_odr* as an example, it indicates a set of *EQUIVALENT* globals
that can be merged at link-time. However, the semantic of 
*EQUIVALENT*-functions includes parameters. Changing parameters breaks
the assumption.

  Thank John McCall for help, especially for the explanation of subtle
difference between linkage types.

  rdar://11546243


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192302 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 17:21:44 +00:00
Venkatraman Govindaraju
3b73dea538 [Sparc] Disable tail call optimization for sparc64. 
This patch fixes PR17506.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192294 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 12:50:39 +00:00
Elena Demikhovsky
50dc2ad46c AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 08:16:14 +00:00
Tim Northover
d29bae8bc9 AArch64: enable MISched by default. 
Substantial SelectionDAG scheduling is going away soon, and is
interfering with Hao's attempts to implement LDn/STn instructions, so
I say we make the leap first.

There were a few reorderings (inevitably) which broke some tests. I
tried to replace them with CHECK-DAG variants mostly, but some too
complex for that to be useful and I just reordered them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192282 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 07:53:57 +00:00
Tim Northover
ccb06ae8f3 AArch64: migrate ADRP relaxation test to be llvm-mc only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192281 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 07:53:49 +00:00
Craig Topper
b96a393b09 Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192266 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 02:18:34 +00:00
NAKAMURA Takumi
8bb2a23a1d llvm/test/LTO should run also on cygwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192262 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 01:07:31 +00:00
Manman Ren
456e5e5521 Debug Info: In DIBuilder, the context field of a DICompositeType is updated 
to use DIScopeRef.

A paired commit at clang is required due to changes to DIBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192256 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 00:17:04 +00:00
Manman Ren
b6f74f0668 Debug Info: In DIBuilder, the context fields of a static member and a 
typedef are updated to use DIScopeRef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192254 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 23:49:38 +00:00
Manman Ren
c1e2b2582c Debug Info: In DIBuilder, the derived-from field of DICompositeType 
is updated to use DITypeRef.

A paired commit at clang is required due to changes to DIBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192251 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 23:28:51 +00:00
Manman Ren
78c2f9b8cf Debug Info: In DIBuilder, the derived-from field of DIDerivedType 
is updated to use DITypeRef.

A paired commit at clang is required due to changes to DIBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192246 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 22:56:31 +00:00
Chad Rosier
c976500793 [AArch64] Add support for NEON scalar floating-point reciprocal estimate, 
reciprocal exponent, and reciprocal square root estimate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 22:09:04 +00:00
Chad Rosier
3dfe644f7b [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point 
convert instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 20:43:30 +00:00
Manman Ren
875857953f Debug Info: update testing to reflect r192018. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192224 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 20:06:43 +00:00
Reed Kotler
78f8339f35 Add fabsf to the list of inlined functions; otherwise 
Mips16 will try and create a stub for it and this will
result in a link error because that function does not exist in libc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192223 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 19:55:01 +00:00
Matt Arsenault
194d437f11 Add some xfaild R600 tests. 
These are bugs to fix later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192212 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 18:06:36 +00:00
Reed Kotler
b359bda93d Let rotr and bswap be handled by expansion for Mips16 since we don't 
have native instructions for this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192207 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 17:32:33 +00:00
Craig Topper
75172ad6f2 Fix a typo in the mattr part of the run line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192174 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 06:12:26 +00:00
Craig Topper
d8feb1f9a5 Explicitly disable AVX on a bunch of tests so they won't fail on AVX machines post r192171. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192173 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 06:06:57 +00:00
Craig Topper
b9bc43852c Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 05:53:50 +00:00
Adrian Prantl
d79f6f786a typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192158 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 02:30:54 +00:00
Adrian Prantl
a204ac9e90 typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192157 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 02:28:20 +00:00
Adrian Prantl
82c7414448 Reduce testcase from 1r92011. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192156 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 02:21:44 +00:00
Akira Hatanaka
d56cba0b4b [mips] Test case for r192124. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192135 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 21:32:57 +00:00
Arnold Schwaighofer
1ee3c0008b LoopVectorize: External uses must use the last value in a reduction cycle 
Otherwise, we don't perform operations that would have been performed on
the scalar version.

Fixes PR17498.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192133 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 21:05:43 +00:00
Reed Kotler
42be15fcbe Add Mips16 patterns for sign extend byte and sign extend halfword. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192130 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 20:46:19 +00:00