Commit Graph

93532 Commits

Author SHA1 Message Date
Richard Trieu
a785a7bf51 Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 23:06:23 +00:00
Ulrich Weigand
bbeba2c200 [PowerPC] Fix 32-bit PowerPC TLS relocs
Some TLS relocs were copied incorrectly from ppc64 to ppc32,
and some were missing completely.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 22:27:57 +00:00
David Blaikie
a35ae96291 PR16493: DebugInfo with TLS on PPC crashing due to invalid relocation
Restrict the current TLS support to X86 ELF for now. Test that we don't
produce it on PPC & we can flesh that test case out with the right thing
once someone implements it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185389 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 21:45:25 +00:00
Ulrich Weigand
1307d8300f [PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 21:40:54 +00:00
Chad Rosier
bde84a96ea Add a newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185385 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 21:31:10 +00:00
Manman Ren
89c83b7632 Debug Info: clean up usage of Verify.
No functionality change. It should suffice to check the type of a debug info
metadata, instead of calling Verify.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185383 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 21:02:01 +00:00
Bill Schmidt
c38c1d135c Index: test/CodeGen/PowerPC/reloc-align.ll
===================================================================
--- test/CodeGen/PowerPC/reloc-align.ll	(revision 0)
+++ test/CodeGen/PowerPC/reloc-align.ll	(revision 0)
@@ -0,0 +1,34 @@
+; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s
+
+; This test verifies that the peephole optimization of address accesses
+; does not produce a load or store with a relocation that can't be
+; satisfied for a given instruction encoding.  Reduced from a test supplied
+; by Hal Finkel.
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.S1 = type { [8 x i8] }
+
+@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1
+
+; Function Attrs: nounwind readonly
+define signext i32 @main() #0 {
+entry:
+  %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*))
+; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l
+  ret i32 %call
+}
+
+; Function Attrs: nounwind readonly
+define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 {
+entry:
+  %0 = bitcast %struct.S1* %p_91 to i64*
+  %bf.load = load i64* %0, align 1
+  %bf.shl = shl i64 %bf.load, 26
+  %bf.ashr = ashr i64 %bf.shl, 54
+  %bf.cast = trunc i64 %bf.ashr to i32
+  ret i32 %bf.cast
+}
+
+attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
--- lib/Target/PowerPC/PPCAsmPrinter.cpp	(revision 185327)
+++ lib/Target/PowerPC/PPCAsmPrinter.cpp	(working copy)
@@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI
       OutStreamer.EmitRawText(StringRef("\tmsync"));
       return;
     }
+    break;
+  case PPC::LD:
+  case PPC::STD:
+  case PPC::LWA: {
+    // Verify alignment is legal, so we don't create relocations
+    // that can't be supported.
+    // FIXME:  This test is currently disabled for Darwin.  The test
+    // suite shows a handful of test cases that fail this check for
+    // Darwin.  Those need to be investigated before this sanity test
+    // can be enabled for those subtargets.
+    if (!Subtarget.isDarwin()) {
+      unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
+      const MachineOperand &MO = MI->getOperand(OpNum);
+      if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4)
+        llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
+    }
+    // Now process the instruction normally.
+    break;
   }
+  }
 
   LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
   OutStreamer.EmitInstruction(TmpInst);
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp	(revision 185327)
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp	(working copy)
@@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() {
       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
         SDLoc dl(GA);
         const GlobalValue *GV = GA->getGlobal();
+        // We can't perform this optimization for data whose alignment
+        // is insufficient for the instruction encoding.
+        if (GV->getAlignment() < 4 &&
+            (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
+             StorageOpcode == PPC::LWA)) {
+          DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
+          continue;
+        }
         ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
       } else if (ConstantPoolSDNode *CP =
                  dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185380 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:52:27 +00:00
Chad Rosier
e29e2afc73 [ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
tablegen enum values.  This should be the last fix due to fallout from r185094.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185379 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:49:23 +00:00
Lang Hames
781f5b3953 Make PBQP require/preserve MachineLoopInfo - the spiller requires it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185378 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:47:47 +00:00
Sean Silva
2f8a1769e4 [docs] Amend confusing title
"Writing an LLVM Compiler Backend" can be misinterpreted as meaning
"backend" in the sense of "using LLVM as a backend for your compiler for
your new language". This new name is less ambiguous.

As a bonus, this brings the title in line with the file name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185377 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:45:12 +00:00
Akira Hatanaka
5112243aec [mips] Reverse the order of source operands of shift and rotate instructions that
have three register operands.

No intended functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:39:53 +00:00
Ulrich Weigand
3bd2b92267 [PowerPC] Also add "msync" alias
This adds an alias for "msync" (which is used on Book E
systems instead of "sync").



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185375 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:39:50 +00:00
Akira Hatanaka
db8e0bbedb [mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:31:44 +00:00
Akira Hatanaka
ae99e41ff4 [mips] Fix test case to check that mips64 instructions are generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185371 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:18:58 +00:00
Anton Korobeynikov
4ba16b2c60 Really fix the test. Sorry for the breakage...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 19:51:36 +00:00
Anton Korobeynikov
5c60a07285 Fix the test which relies on uncommitted change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185368 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 19:50:31 +00:00
Cameron Zwarich
f807a6ee3a Fix the build after r185363. Use llvm::next instead of raw next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185367 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 19:49:48 +00:00
Anton Korobeynikov
27253f5edd Add jump tables handling for MSP430.
Patch by Job Noorman!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 19:44:44 +00:00
Cameron Zwarich
03fae50cfa Fix PR16508.
When phis get lowered, destination copies are inserted using an iterator that is
determined once for all phis in the block, which BuildMI interprets as a request
to insert an instruction directly before the iterator. In the case of a cyclic
phi, source copies may also be inserted directly before this iterator, which can
cause source copies to be inserted before destination copies. The fix is to keep
an iterator to the last phi and then advance it while lowering each phi in order
to insert destination copies directly after the phis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 19:42:46 +00:00
Hal Finkel
b5f7b0f978 Don't form PPC CTR loops for over-sized exit counts
Although you can't generate this from C on PPC64, if you have a loop using a
64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had
been cauing the PPCCTRLoops pass to assert.

Thanks to Joerg Sonnenberger for providing a test case!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 19:34:59 +00:00
Tim Northover
6711fc28a4 AArch64: correct CodeGen of MOVZ/MOVK combinations.
According to the AArch64 ELF specification (4.6.8), it's the
assembler's responsibility to make sure the shift amount is correct in
relocated MOVZ/MOVK instructions.

This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF
(which happened to work out well for JIT tests). This commit should
make us compliant in this area.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 19:23:10 +00:00
Matt Beaumont-Gay
1a84066b8c (1) Add ".test" to test/Other/lit.local.cfg, so llvm-cov.test is actually run.
(2) Rename llvm-cov test inputs so the string "llvm-cov" doesn't get
substituted by lit within the input filenames on the RUN line.
(3) XFAIL llvm-cov.test because it asserts:
include/llvm/ADT/SmallVector.h:140: reference llvm::SmallVectorTemplateCommon<llvm::GCOVBlock *, void>::operator[](unsigned int) [T = llvm::GCOVBlock *]: Assertion `begin() + idx < end()' failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 18:58:53 +00:00
Tim Northover
40d0492cde Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")
Turns out I'd misread the architecture reference manual and thought
that was a load/store-store barrier, when it's not.

Thanks for pointing it out Eli!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 18:37:33 +00:00
Manman Ren
c7b61c638b Debug Info: Scope of a DebugLoc should not be null.
No functionality change. Remove handling for the null case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 18:20:30 +00:00
Ulrich Weigand
222e781d92 [PowerPC] Fix @got references to local symbols
A @got reference must always result in a relocation, so that
the linker has a chance to set up the GOT entry, even if the
symbol happens to be local.

Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces
a relocation to be emitted for GOT references.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 18:19:56 +00:00
Ulrich Weigand
62c1baf8b5 [PowerPC] Add "wait" instruction
This adds the "wait" instruction and its extended mnemonics.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185350 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 17:21:23 +00:00
Ulrich Weigand
c0a6b981de [PowerPC] Support "eieio" instruction
This adds support for the "eieio" instruction to
the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 17:06:26 +00:00
Michael Gottesman
48b4d4f647 Added c++ mode selector to head of SelectionDAGBuilder.h so editors open it in c++ mode instead of c mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185348 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 16:53:41 +00:00
Ulrich Weigand
4c1d023de8 [PowerPC] Add some existing instructions to ppc64-encoding-bookII.s
The test case had a couple of FIXMEs where the instruction is in
fact already supported by the back-end.  In some other case, while
the generic form of the instruction is not yet supported, a
specialized form is.  This adds tests for those already supported
instructions / instruction forms.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185347 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 16:52:55 +00:00
Ulrich Weigand
af679a2292 [PowerPC] Add variants of "sync" instruction
This adds support for the "sync $L" instruction with operand,
and provides aliases for "lwsync" and "ptesync".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185344 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 16:37:52 +00:00
Tim Northover
d59fc0af0a ARM: relax the atomic release barrier to "dmb ishst"
I believe the full "dmb ish" barrier is not required to guarantee release
semantics for atomic operations. The weaker "dmb ishst" prevents previous
operations being reordered with a store executed afterwards, which is enough.

A key point to note (fortunately already correct) is that this barrier alone is
*insufficient* for sequential consistency, no matter how liberally placed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 14:48:48 +00:00
Justin Holewinski
728af3d574 [NVPTX] Add support for module-scope inline asm
Since we were explicitly not calling AsmPrinter::doInitialization,
any module-scope inline asm was not being printed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 13:00:14 +00:00
Justin Holewinski
1fd09172bb [NVPTX] We dont use NVBuiltin anymore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185335 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 12:59:08 +00:00
Justin Holewinski
c676590614 [NVPTX] Cut down on physical register defs
We are using virtual registers throughout now, but we still need
to keep a few physical registers per class around to keep the
infrastructure happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 12:59:06 +00:00
Justin Holewinski
fc32eb472a [NVPTX] 64-bit ADDC/ADDE are not legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185333 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 12:59:04 +00:00
Justin Holewinski
be08c60533 [NVPTX] Fix vector loads from parameters that span multiple loads, and fix some typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185332 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 12:59:01 +00:00
Justin Holewinski
03e5bb2c87 [NVPTX] Handle signext/zeroext attributes properly
Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value.

Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 12:58:58 +00:00
Justin Holewinski
8834184a46 [NVPTX] Add support for native SIGN_EXTEND_INREG where available
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 12:58:56 +00:00
Justin Holewinski
9bc8feeb4f [NVPTX] Add isel patterns for [reg+offset] form of ldg/ldu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185329 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 12:58:52 +00:00
Justin Holewinski
30b13ebd0b [NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185328 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 12:58:48 +00:00
NAKAMURA Takumi
d212db0cac llvm-symbolizer: Recognize a drive letter on win32. Then "REQUIRES: shell" can be removed.
FIXME: Could we use llvm::sys::Path here?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185322 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 09:51:42 +00:00
Serge Pavlov
f04f8b4f77 Added the test missed from r185080.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185316 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 09:02:33 +00:00
Sylvestre Ledru
ba62f2f1bf The build system is currently miss-identifying GNU/kFreeBSD as FreeBSD.
This kind of simplification is sometimes useful, but in general it's not correct. 

As GNU/kFreeBSD is an hybrid system, for kernel-related issues we want to match the
build definitions used for FreeBSD, whereas for userland-related issues we want to
match the definitions used for other systems with Glibc.

The current modification adjusts the build system so that they can be distinguished,
and explicitly adds GNU/kFreeBSD to the build checks in which it belongs.

Fixes bug #16444.

Patch by Robert Millan in the context of Debian.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185311 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 08:07:52 +00:00
Arnold Schwaighofer
c14380d195 LoopVectorize: Math functions only read rounding mode
Math functions are mark as readonly because they read the floating point
rounding mode. Because we don't vectorize loops that would contain function
calls that set the rounding mode it is safe to ignore this memory read.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185299 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 00:54:44 +00:00
Vincent Lejeune
c36a8d2b3d R600: Fix an unitialized variable in R600InstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185294 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-30 21:44:06 +00:00
Ahmed Bougacha
27bf6e96a7 X86: POP*rmm: move address operand to (ins) from (outs).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185292 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-30 20:44:50 +00:00
Stephen Lin
3f4385a0b6 DeadArgumentElimination: keep return value on functions that have a live argument with the 'returned' attribute (rather than generate invalid IR); however, if both can be eliminated, both will be
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185290 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-30 20:26:21 +00:00
Benjamin Kramer
80c070493d ConstantFold: Check that truncating the other side is safe under a sext when trying to remove a sext from a compare.
Fixes PR16462.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-30 13:47:43 +00:00
David Majnemer
58b6dc032a ValueTracking: Teach isKnownToBeAPowerOfTwo about (ADD X, (XOR X, Y)) where X is a power of two
This allows us to simplify urem instructions involving the add+xor to
turn into simpler math.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185272 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-29 23:44:53 +00:00
Benjamin Kramer
bebf6222f6 NVPTX: Fold otherwise unused variable into assert.
Avoids unused variable warnings in release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185271 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-29 22:51:12 +00:00