Commit Graph

92 Commits

Author SHA1 Message Date
Andrew Trick
83a8031336 Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 18:22:31 +00:00
Andrew Trick
4815d56bb2 ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 03:17:40 +00:00
Evan Cheng
37fefc20d3 Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 19:09:48 +00:00
David Greene
05bce0beee Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 22:43:06 +00:00
David Greene
f37dd02f77 [AVX] Constify Inits
Make references to Inits const everywhere.  This is the final step
before making them unique.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 19:07:05 +00:00
Benjamin Kramer
5196c12e9f Add a new field to MCOperandInfo that contains information about the type of the Operand.
- The actual values are from the MCOI::OperandType enum.
- Teach tblgen to read it from the instruction definition.
- This is a better implementation of the hacks in edis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:47:18 +00:00
Eric Christopher
d568b3f552 Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 23:06:52 +00:00
David Greene
d4a9066c93 [AVX] Make Inits Foldable
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 18:25:51 +00:00
Jim Grosbach
e727d67c58 Add isCodeGenOnly value to the CodeGenInstruction class.
So users of a CGI don't have to look up the value directly from the original
Record; just like the rest of the convenience values in the class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:48:02 +00:00
Jim Grosbach
806fcc040e Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 21:33:38 +00:00
Chris Lattner
a90dbc133f change OperandsSignature to use SmallVector<char> instead of std::vector<string>
since the strings are always exactly one character, and there are usually only 2-3 operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 22:24:13 +00:00
Evan Cheng
0f040a258f - Add "Bitcast" target instruction property for instructions which perform
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 05:09:26 +00:00
Jim Grosbach
0c4d44aa7a Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 17:32:49 +00:00
Bob Wilson
a49c7dfb36 Improve the AsmMatcher's ability to handle suboperands.
When an operand class is defined with MIOperandInfo set to a list of
suboperands, the AsmMatcher has so far required that operand to also define
a custom ParserMatchClass, and InstAlias patterns have not been able to
set the individual suboperands separately.  This patch removes both of those
restrictions.  If a "compound" operand does not override the default
ParserMatchClass, then the AsmMatcher will now parse its suboperands
separately.  If an InstAlias operand has the same class as the corresponding
compound operand, then it will be handled as before; but if that check fails,
TableGen will now try to match up a sequence of InstAlias operands with the
corresponding suboperands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26 19:44:55 +00:00
Bob Wilson
5e8f2a65ca Precompute InstAlias operand mapping to result instruction operand indices.
There should be no functional change from this, but I think it's simpler this
way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123931 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20 18:38:02 +00:00
Evan Cheng
c4af4638df Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 20:13:28 +00:00
Chris Lattner
90fd797dc7 add (and document) the ability for alias results to have
fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118352 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:57:21 +00:00
Chris Lattner
98c870f87b generalize alias support to allow the result of an alias to
add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:25:43 +00:00
Chris Lattner
5bde734598 fix a bug where we had an implicit assumption that the
result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 08:20:59 +00:00
Chris Lattner
662e5a30e8 Reimplement BuildResultOperands to be in terms of the result instruction's
operand list instead of the operand list redundantly declared on the alias
or instruction.

With this change, we finally remove the ins/outs list on the alias.  Before:
  def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
                  "movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
  def : InstAlias<"movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;

This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:14:44 +00:00
Chris Lattner
225549f775 disolve a hack, having CodeGenInstAlias decode the alias in the .td
file instead of the asmmatcher.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118324 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 06:39:47 +00:00
Chris Lattner
9b0d4bfca0 rewrite EmitConvertToMCInst to iterate over the MCInst operands,
filling them in one at a time.  Previously this iterated over the
asmoperands, which left the problem of "holes".  The new approach
simplifies things.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:55:03 +00:00
Chris Lattner
b501d4f673 Implement enough of the missing instalias support to get
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:34:34 +00:00
Chris Lattner
c76e80ded7 define a new CodeGenInstAlias. It has an asmstring and operand list for now,
todo: the result field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:05:41 +00:00
Chris Lattner
c240bb0ede factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:03:32 +00:00
Chris Lattner
79b3cddfa2 avoid needless throw/catch/rethrow, stringref'ize some simple stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 03:19:09 +00:00
Chris Lattner
f780811456 eliminate the old InstFormatName which is always "AsmString",
simplify CodeGenInstruction. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 02:15:23 +00:00
Chris Lattner
4d43d0fd99 move FlattenVariants out of AsmMatcherEmitter into a shared
CodeGenInstruction::FlattenAsmStringVariants method.  Use it
to simplify the code in AsmWriterInst, which now no longer 
needs to worry about variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 01:07:14 +00:00
Jim Grosbach
5013f7469e Allow targets to optionally specify custom binary encoder functions for
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:21:57 +00:00
Jim Grosbach
01855071e2 When figuring out which operands match which encoding fields in an instruction,
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116211 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:25:51 +00:00
Jim Grosbach
9ed2cee105 trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 18:09:59 +00:00
Owen Anderson
f523e476c2 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:45:25 +00:00
Owen Anderson
5716180b1a Add an TargetInstrDesc bit to indicate that a given instruction is a conditional move.
Not intended functionality change, as nothing uses this yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 22:44:10 +00:00
Bill Wendling
73739d0bf1 Add back in r109901, which adds a Compare flag to the target instructions. It's
useful after all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-08 01:49:35 +00:00
Bill Wendling
5b55ff0c15 Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn't
need the Compare flag after all.

--- Reverse-merging r109901 into '.':
U    include/llvm/Target/TargetInstrDesc.h
U    include/llvm/Target/Target.td
U    utils/TableGen/InstrInfoEmitter.cpp
U    utils/TableGen/CodeGenInstruction.cpp
U    utils/TableGen/CodeGenInstruction.h



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110424 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 01:36:09 +00:00
Bill Wendling
1844b1a5a4 Add a "Compare" flag to the target instruction descriptor. This will be used
later to identify and possibly remove superfluous compare instructions -- those
that are testing for and setting a status flag that should already be set.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 22:48:39 +00:00
Chris Lattner
9414ae5291 hoist some funky logic into CodeGenInstruction
from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:09:24 +00:00
Chris Lattner
f506b6b471 capture implicit uses and defs in CodeGenInstruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:42:03 +00:00
Chris Lattner
cedef1ccf0 remove some code that was working around old sparc v9 backend bugs.
Add checking that the input/output operand list in spelled right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98865 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:50:52 +00:00
Dan Gohman
bc9d98b52d The mayHaveSideEffects flag is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27 23:47:46 +00:00
Chris Lattner
e555c9f4a5 work around a gcc bug with -Wuninitialized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10 21:22:51 +00:00
Chris Lattner
a7d479c7bd Introduce a new CodeGenInstruction::ConstraintInfo class
for representing constraint info semantically instead of
as a c expression that will be blatted out to the .inc
file.  Fix X86RecognizableInstr to use this instead of
parsing C code :).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10 01:45:28 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29 18:10:34 +00:00
Evan Cheng
799d697bf8 Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When
set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 08:21:18 +00:00
Dan Gohman
15511cf166 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 18:15:48 +00:00
Bill Wendling
8370d38ade Add a flag to indicate that an instruction is as cheap (or cheaper) than a move
instruction to execute. This can be used for transformations (like two-address
conversion) to remat an instruction instead of generating a "move"
instruction. The idea is to decrease the live ranges and register pressure and
all that jazz.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 22:54:52 +00:00
Evan Cheng
20ccded7de Remove isImplicitDef TargetInstrDesc flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15 00:19:36 +00:00
Chris Lattner
ba7e756c22 Start inferring side effect information more aggressively, and fix many bugs in the
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 07:59:24 +00:00
Chris Lattner
dcc8b4f5d3 add a mayLoad property for machine instructions, a correlary to mayStore.
This is currently not set by anything.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-08 18:05:21 +00:00
Chris Lattner
8f707e15fb rename hasVariableOperands() -> isVariadic(). Add some comments.
Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45687 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 05:19:29 +00:00