Commit Graph

434 Commits

Author SHA1 Message Date
Craig Topper
87802d52e1 Remove unused MachineInstr constructors that don't take a DebugLoc argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-07 23:03:22 +00:00
Michael Liao
6c7ccaa3fd Fix PR11985
- BlockAddress has no support of BA + offset form and there is no way to
  propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
  simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
  support BA + offset addressing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 21:43:09 +00:00
Manman Ren
b720be6a50 Release build: guard dump functions with
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"

No functional change. Update r163339.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 22:23:19 +00:00
Manman Ren
77e300e8f0 Release build: guard dump functions with "ifndef NDEBUG"
No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 19:06:06 +00:00
Chad Rosier
2f1d815479 Cleanup a few magic numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163263 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 22:40:13 +00:00
Chad Rosier
77fffa6fdd [ms-inline asm] We only need one bit to represent the AsmDialect in the
MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 22:17:43 +00:00
Chad Rosier
576cd11ab8 [ms-inline asm] Propagate the asm dialect into the MachineInstr representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 21:00:58 +00:00
Jakob Stoklund Olesen
4f1a56ce3c Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 18:44:43 +00:00
Jakob Stoklund Olesen
99c416c9f7 Actually use the MachineOperand field for isRegTiedToDefOperand().
The MachineOperand::TiedTo field was maintained, but not used.

This patch enables it in isRegTiedToDefOperand() and
isRegTiedToUseOperand() which are the actual functions use by the
register allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 18:43:25 +00:00
Jakob Stoklund Olesen
9c13067276 Allow tied uses and defs in different orders.
After much agonizing, use a full 4 bits of precious MachineOperand space
to encode this. This uses existing padding, and doesn't grow
MachineOperand beyond its current 32 bytes.

This allows tied defs among the first 15 operands on a normal
instruction, just like the current MCInstrDesc constraint encoding.
Inline assembly needs to be able to tie more than the first 15 operands,
and gets special treatment.

Tied uses can appear beyond 15 operands, as long as they are tied to a
def that's in range.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163151 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 18:36:28 +00:00
Jakob Stoklund Olesen
94083149fd Add MachineInstr::tieOperands, remove setIsTied().
Manage tied operands entirely internally to MachineInstr. This makes it
possible to change the representation of tied operands, as I will do
shortly.

The constraint that tied uses and defs must be in the same order was too
restrictive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163021 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31 20:50:53 +00:00
Jakob Stoklund Olesen
e941df5e35 Don't use MCInstrDesc flags for implicit operands.
When a MachineInstr is constructed, its implicit operands are added
first, then the explicit operands are inserted before the implicits.

MCInstrDesc has oprand flags like early clobber and operand ties that
apply to the explicit operands.

Don't look at those flags when the implicit operands are first added in
the explicit operands's positions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 14:39:06 +00:00
Jakob Stoklund Olesen
f036f7a1e7 Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().
Ordered memory operations are more constrained than volatile loads and
stores because they must be ordered with respect to all other memory
operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 21:19:21 +00:00
Jakob Stoklund Olesen
0d75858395 Don't move normal loads across volatile/atomic loads.
It is technically allowed to move a normal load across a volatile load,
but probably not a good idea.

It is not allowed to move a load across an atomic load with
Ordering > Monotonic, and we model those with MOVolatile as well.

I recently removed the mayStore flag from atomic load instructions, so
they don't need a pseudo-opcode. This patch makes up for the difference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162857 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 20:48:45 +00:00
Jakob Stoklund Olesen
699ac04951 Maintain a vaild isTied bit as operands are added and removed.
The isTied bit is set automatically when a tied use is added and
MCInstrDesc indicates a tied operand. The tie is broken when one of the
tied operands is removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:37:58 +00:00
Jakob Stoklund Olesen
4ba6916a98 Add a MachineOperand::isTied() flag.
While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.

Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.

The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.

Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.

Adding a predicate to:

  %vreg0<def> = ADD %vreg1, %vreg2

Will look like:

  %vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>

The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.

This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 18:34:41 +00:00
Jakob Stoklund Olesen
190e342cbc Don't allow TargetFlags on MO_Register MachineOperands.
Register operands are manipulated by a lot of target-independent code,
and it is not always possible to preserve target flags. That means it is
not safe to use target flags on register operands.

None of the targets in the tree are using register operand target flags.
External targets should be using immediate operands to annotate
instructions with operand modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 18:05:48 +00:00
Jakob Stoklund Olesen
d6397eba23 Also update MRI use lists when changing a use to a def and vice versa.
This was the cause of the buildbot failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161643 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 00:21:26 +00:00
Jakob Stoklund Olesen
ff2b99afc8 Move use list management into MachineRegisterInfo.
Register MachineOperands are kept in linked lists accessible via MRI's
reg_iterator interfaces. The linked list management was handled partly
by MachineOperand methods, partly by MRI methods.

Move all of the list management into MRI, delete
MO::AddRegOperandToRegInfo() and MO::RemoveRegOperandFromRegInfo().

Be more explicit about handling the cases where an MRI pointer isn't
available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 22:49:37 +00:00
Jakob Stoklund Olesen
0b40d09ff6 Add a new kind of MachineOperand: MO_TargetIndex.
A target index operand looks a lot like a constant pool reference, but
it is completely target-defined. It contains the 8-bit TargetFlags, a
32-bit index, and a 64-bit offset. It is preserved by all code generator
passes.

TargetIndex operands can be used to carry target-specific information in
cases where immediate operands won't suffice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161441 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 18:56:39 +00:00
Chandler Carruth
d862d697d2 Finish fixing the MachineOperand hashing, providing a nice modern
hash_value overload for MachineOperands. This addresses a FIXME
sufficient for me to remove it, and cleans up the code nicely too.

The important changes to the hashing logic:
- TargetFlags are now included in all of the hashes. These were complete
  missed.
- Register operands have their subregisters and whether they are a def
  included in the hash.
- We now actually hash all of the operand types. Previously, many
  operand types were simply *dropped on the floor*. For example:
  - Floating point immediates
  - Large integer immediates (>64-bit)
  - External globals!
  - Register masks
  - Metadata operands
- It removes the offset from the block-address hash; I'm a bit
  suspicious of this, but isIdenticalTo doesn't consider the offset for
  black addresses.

Any patterns involving these entities could have triggered extreme
slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs
you think might be closed now... I'm looking myself, but I may miss
them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 11:06:22 +00:00
Chandler Carruth
b8087451ca The hash function for MI expressions, used by MachineCSE, is really
broken. This patch fixes the superficial problems which lead to the
intractably slow compile times reported in PR13225.

The specific issue is that we were failing to include the *offset* of
a global variable in the hash code. Oops. This would in turn cause all
MIs which were only distinguishable due to operating on different
offsets of a global variable to produce identical hash functions. In
some of the test cases attached to the PR I saw hash table activity
where there were O(1000) probes-per-lookup *on average*. A very few
entries were responsible for most of these probes.

There is still quite a bit more to do here. The ad-hoc layering of data
in MachineOperands makes them *extremely* brittle to hash correctly.
We're missing quite a few other cases, the only ones I've fixed here are
the specific MO types which were allowed through the assert() in
getOffset().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 10:03:57 +00:00
Jakob Stoklund Olesen
33a537a5c4 Allow trailing physreg RegisterSDNode operands on non-variadic instructions.
Also allow trailing register mask operands on non-variadic both
MachineSDNodes and MachineInstrs.

The extra physreg RegisterSDNode operands are added to the MI as
<imp-use> operands. This makes it possible to have non-variadic call
instructions.

Call and return instructions really are non-variadic, the argument
registers should only be used implicitly - they are not part of the
encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04 23:53:23 +00:00
Bill Wendling
0bcbd1df7a Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h.

The reasoning is because the DebugInfo module is simply an interface to the
debug info MDNodes and has nothing to do with analysis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28 00:05:13 +00:00
Andrew Trick
d88d27868b MachineInstr::eraseFromParent fix for removing bundled instrs.
Patch by Ivan Llopard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05 21:44:23 +00:00
Jakob Stoklund Olesen
396618b43a Switch all register list clients to the new MC*Iterator interface.
No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01 23:28:30 +00:00
Jakob Stoklund Olesen
275fd2523e Remove some redundant tests.
An empty list is not represented as a null pointer. Let TRI do its own
shortcuts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157702 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 18:38:56 +00:00
Jakob Stoklund Olesen
397fc4874e Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 22:10:26 +00:00
Jakob Stoklund Olesen
41afb9da2c Remove extra comma in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156219 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:53:26 +00:00
Jakob Stoklund Olesen
3429c7571e Print <def,read-undef> to avoid confusion.
The <undef> flag on a def operand only applies to partial register
redefinitions. Only print the flag when relevant, and print it as
<def,read-undef> to make it clearer what it means.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155239 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 21:45:33 +00:00
Rafael Espindola
95d594cac3 Teach CodeGen's version of computeMaskedBits to understand the range metadata.
This is the CodeGen equivalent of r153747. I tested that there is not noticeable
performance difference with any combination of -O0/-O2 /-g when compiling
gcc as a single compilation unit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 18:14:00 +00:00
Benjamin Kramer
85f9cef27e MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.
This is particularly helpful as both arguments tend to be constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 17:03:45 +00:00
Benjamin Kramer
861ea230a7 Limit the number of memory operands in MachineInstr to 2^16 and store the number in padding.
Saves one machine word on MachineInstr (88->80 bytes on x86_64, 48->44 on i386).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152930 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 16:39:27 +00:00
Craig Topper
fac2598149 Use uint16_t to store instruction implicit uses and defs. Reduces static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08 08:22:45 +00:00
Chandler Carruth
b53a1d67b1 Try to clarify this comment some.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 10:13:40 +00:00
Chandler Carruth
fc22625eb0 Remove another outbreak of customized (and completely broken) hashing.
This one is particularly annoying because the hashing algorithm is
highly specialized, with a strange "equivalence" definition that subsets
the fields involved.

Still, this looks at the exact same set of data as the old code, but
without bitwise or-ing over parts of it and other mixing badness. No
functionality changed here. I've left a substantial fixme about the fact
that there is a cleaner and more principled way to do this, but it
requires making the equality definition actual stable for particular
types...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 09:39:46 +00:00
Craig Topper
e4fd907e72 Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 10:43:23 +00:00
Jakob Stoklund Olesen
741981adf3 Move getBundleStart() into MachineInstrBundle.h.
This allows the function to be inlined, and makes it suitable for use in
getInstructionIndex().

Also provide a const version. C++ is great for touch typing practice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 01:26:01 +00:00
Lang Hames
00195d828b Reverse iterator - should be incrementing rather than decrementing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 01:54:11 +00:00
Lang Hames
cc2037be2c Make LiveIntervals::handleMove() bundle aware.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 23:21:33 +00:00
Jakob Stoklund Olesen
1cf8b0f2a5 Handle regmasks in findRegisterDefOperandIdx().
Only accept register masks when looking for an 'overlapping' def. When
Overlap is not set, the function searches for a proper definition of
Reg.

This means MI->modifiesRegister() considers register masks, but
MI->definesRegister() doesn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150529 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14 23:49:37 +00:00
Benjamin Kramer
c667ba69ac Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.
Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10 13:18:44 +00:00
Andrew Trick
99a7a13f4a Added MachineInstr::isBundled() to check if an instruction is part of a bundle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 02:17:25 +00:00
Jakob Stoklund Olesen
77180e0b40 Handle register mask operands in setPhysRegsDeadExcept().
Calls that use register mask operands don't have implicit defs for
returned values.  The register mask operand handles the call clobber,
but it always behaves like a set of dead defs.

Add live implicit defs for any implicitly defined physregs that are
actually used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149715 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:23:14 +00:00
Jakob Stoklund Olesen
a37818dbb1 ArrayRef'ize MI::setPhysRegsDeadExcept().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149709 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 20:43:39 +00:00
Jakob Stoklund Olesen
59cb77fb11 Handle all live physreg defs in the same place.
SelectionDAG has 4 different ways of passing physreg defs to users.
Collect all of the uses at the same time, and pass all of them to
MI->setPhysRegsDeadExcept() to mark the remaining defs dead.

The setPhysRegsDeadExcept() function will soon add the required
implicit-defs to instructions with register mask operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 20:43:35 +00:00
Jakob Stoklund Olesen
478a8a02bc Require non-NULL register masks.
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 23:52:57 +00:00
Jakob Stoklund Olesen
1a96c91431 Clear kill flags before propagating a copy.
The live range of the source register may be extended when a redundant
copy is eliminated. Make sure any kill flags between the two copies are
cleared.

This fixes PR11765.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 17:52:15 +00:00
Jakob Stoklund Olesen
7739cad69d Add a new kind of MachineOperand: MO_RegisterMask.
Register masks will be used as a compact representation of large clobber
lists.  Currently, an x86 call instruction has some 40 operands
representing call-clobbered registers.  That's more than 1kB of useless
operands per call site.

A register mask operand references a bit mask of call-preserved
registers, everything else is clobbered.  The bit mask will typically
come from TargetRegisterInfo::getCallPreservedMask().

By abandoning ImplicitDefs for call-clobbered registers, it also becomes
possible to share call instruction descriptions between calling
conventions, and we can get rid of the WINCALL* instructions.

This patch introduces the new operand kind.  Future patches will add
RegMask support to target-independent passes before finally the fixed
clobber lists can be removed from call instruction descriptions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 19:22:00 +00:00
Chandler Carruth
732f05c41f Add 'llvm_unreachable' to passify GCC's understanding of the constraints
of several newly un-defaulted switches. This also helps optimizers
(including LLVM's) recognize that every case is covered, and we should
assume as much.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10 18:08:01 +00:00