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159 Commits

Author SHA1 Message Date
Robert Khasanov
aac33cfc08 [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features. 
Enabling HasAVX512{DQ,BW,VL} predicates.
Adding VK2, VK4, VK32, VK64 masked register classes.
Adding new types (v64i8, v32i16) to VR512.
Extending calling conventions for new types (v64i8, v32i16)

Patch by Zinovy Nis <zinovy.y.nis@intel.com>
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213545 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-21 14:54:21 +00:00
Adam Nemet
6ae2941874 [X86] AVX512: Add disassembler support for compressed displacement 
There are two parts here.  First is to modify tablegen to adjust the encoding
type ENCODING_RM with the scaling factor.

The second is to use the new encoding types to compute the correct
displacement in the decoder.

Fixes <rdar://problem/17608489>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213281 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-17 17:04:56 +00:00
Craig Topper
095734c578 [C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206254 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-15 07:20:03 +00:00
Craig Topper
df24b19e45 [x86] Simplify disassembler code slightly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202233 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-26 06:01:21 +00:00
Craig Topper
46aa7fb720 [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201767 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-20 07:59:43 +00:00
Craig Topper
fa0cf99585 Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201649 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-19 08:25:02 +00:00
Craig Topper
75116bc27e Put some of the X86 formats in a more logical order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201645 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-19 06:59:13 +00:00
Craig Topper
82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-19 05:34:21 +00:00
Craig Topper
7d2bb38164 Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201538 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-18 00:21:49 +00:00
Craig Topper
1ee7e39dd4 Remove filtering concept from X86 disassembler table generation. It's no longer necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201299 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-13 07:07:16 +00:00
Craig Topper
cfd14e6aea Remove special case filtering for instructions with lock prefix as they are all marked with isCodeGenOnly already. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201216 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-12 08:09:20 +00:00
Craig Topper
56d749a86b Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear from the disassembler table build without custom filtering code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201215 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-12 08:02:29 +00:00
Craig Topper
ced2756280 Recommit r201059 and r201060 with hopefully a fix for its original failure. 
Original commits messages:

Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.

Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201065 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-10 06:55:41 +00:00
Bob Wilson
70ff3e91f7 Revert r201059 and r201060. 
r201059 appears to cause a crash in a bootstrapped build of clang. Craig
isn't available to look at it right now, so I'm reverting it while he
investigates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201064 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-10 05:28:30 +00:00
Craig Topper
a73f0e2d49 Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201060 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-10 01:58:12 +00:00
Craig Topper
d8fdb19a7f Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201059 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-10 00:50:34 +00:00
Craig Topper
6b6dfa5c5a Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-02 09:25:09 +00:00
Craig Topper
3c53b6f1ec Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200625 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-02 07:46:05 +00:00
Craig Topper
1415ca1781 Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200624 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-02 07:08:01 +00:00
Craig Topper
f0b161d774 Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200522 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-31 08:47:06 +00:00
Craig Topper
45b8e5fa49 Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200520 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-31 07:00:55 +00:00
David Woodhouse
674140fc3e ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199806 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 15:08:36 +00:00
David Woodhouse
ccbfd5b18a [x86] Allow address-size overrides for STOS[BWLQ] (PR9385) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199804 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 15:08:21 +00:00
David Woodhouse
db9fa461d7 [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199803 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 15:08:08 +00:00
David Woodhouse
9334b07527 [x86] Fix disassembly of MOV16ao16 et al. 
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199654 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-20 12:02:53 +00:00
Craig Topper
85026d9375 Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199364 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-16 07:36:58 +00:00
Craig Topper
38e6f7301d Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199295 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-15 05:02:02 +00:00
Craig Topper
8e31bc35ec Remove stray comma in enum to satisfy -Wpedantic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199194 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-14 08:07:10 +00:00
Craig Topper
525ae45240 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. 
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199193 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-14 07:41:20 +00:00
David Woodhouse
aab59870a4 [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand 
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-08 12:58:24 +00:00
Craig Topper
c8fd2c57c8 The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198589 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-06 06:57:27 +00:00
Craig Topper
adb7d3b49b Use patterns to remove some duplicate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198550 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 06:55:48 +00:00
Craig Topper
6a69266fed Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198547 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 05:46:38 +00:00
Craig Topper
09104ff9df Remove no longer needed x86 disassembler hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198546 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 05:10:07 +00:00
Craig Topper
01cb7fa977 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198545 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:55:55 +00:00
Craig Topper
2b5dc93948 Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198544 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:32:42 +00:00
Craig Topper
527f132627 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:17:28 +00:00
Craig Topper
e43a0f8015 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198530 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 01:35:51 +00:00
Craig Topper
29d56f68c6 Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198515 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-04 22:29:41 +00:00
Craig Topper
030ceadd69 Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198475 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-04 05:09:27 +00:00
Craig Topper
d573aba8e1 Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198336 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 19:12:10 +00:00
Craig Topper
163868fec5 Remove unused HasFROperands field from disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198332 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 18:44:21 +00:00
Craig Topper
a7133ee752 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198327 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 18:20:48 +00:00
Craig Topper
d4e0bc4316 Remove unnecessary stirng comparison from disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198325 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 17:41:40 +00:00
Craig Topper
e625100c6a Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198323 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 17:28:14 +00:00
Craig Topper
e61c70a085 Remove unused function argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198291 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 03:58:45 +00:00
Craig Topper
5cfd40ccd4 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198284 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 21:52:57 +00:00
Craig Topper
95a3ccdd80 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 15:29:32 +00:00
Elena Demikhovsky
3062a311ac AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 15:12:34 +00:00
Craig Topper
979b2cd2bc Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198276 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 14:22:37 +00:00