6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-01 04:29:57 +00:00
Code Issues Projects Releases Wiki Activity
56,664 Commits 39 Branches 0 Tags 277 MiB
b3732fbabd
Commit Graph

95 Commits

Author SHA1 Message Date
Dan Gohman
ea32d8f465 Remove SIL, DIL, and BPL from the GR8_NOREX allocation order also. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-26 18:30:24 +00:00
Dan Gohman
369d4b4c2e SIL, DIL, BPL, and SPL require a REX prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94558 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-26 18:14:22 +00:00
Sean Callanan
108934c65d Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:01:26 +00:00
Dan Gohman
21313bc62f Add RIP to GR64_NOREX. This fixed a MachineVerifier error when RIP 
is used in an operand which requires GR64_NOREX.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83307 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-05 15:42:08 +00:00
Sean Callanan
38fee0edcf Added a new register class for segment registers 
to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81895 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 18:47:29 +00:00
Dan Gohman
524dab14f4 Minor whitespace tidiness. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77602 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 17:04:07 +00:00
Dan Gohman
68a31c2583 Rename GRAD to GR32_AD, to follow the naming convention of other 
classes. And define its SubRegClassList.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77601 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 17:02:08 +00:00
Dan Gohman
a4714e025d Add a new register class to describe operands that can't be SP, 
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77565 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 01:56:29 +00:00
Dan Gohman
084d1ba5ad Eliminate a bunch of redundant tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77558 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 00:40:42 +00:00
Dan Gohman
7c5f0c5ce9 Use array_endof instead of doing it manually. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77553 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 00:10:18 +00:00
David Greene
d94c101abb Add a 256-bit register class and YMM registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74469 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 22:50:51 +00:00
Chris Lattner
c4233af200 add %rip to the GR64 register class. Lets avoid allocating it to anything though! :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74328 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 21:25:00 +00:00
Dan Gohman
4af325d1b4 Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these 
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!

Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70211 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-27 16:41:36 +00:00
Dan Gohman
6241762c5a Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD, 
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-27 16:33:14 +00:00
Dan Gohman
aaa1fdb271 Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble with 
the local register allocator.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69115 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-15 00:10:16 +00:00
Dan Gohman
a2f3703efd GR8_NOREX can contain the H registers, since they don't require 
REX prefixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69108 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-15 00:00:48 +00:00
Evan Cheng
b3f5bfe37f Some of GR8_NOREX registers are only available in 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69049 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-14 16:57:43 +00:00
Dan Gohman
21e3dfbc86 Implement x86 h-register extract support. 
- Add patterns for h-register extract, which avoids a shift and mask,
   and in some cases a temporary register.
 - Add address-mode matching for turning (X>>(8-n))&(255<<n), where
   n is a valid address-mode scale value, into an h-register extract
   and a scaled-offset address.
 - Replace X86's MOV32to32_ and related instructions with the new
   target-independent COPY_TO_SUBREG instruction.

On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.

These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-13 16:09:41 +00:00
Dan Gohman
3cf9b3e455 Fix copy+pastos in comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68958 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-13 15:28:29 +00:00
Dan Gohman
ee30047386 List the l registers before h registers, for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68954 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-13 15:18:42 +00:00
Rafael Espindola
094fad37b9 Re-apply 68552. 
Tested by bootstrapping llvm-gcc and using that to build llvm.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-08 21:14:34 +00:00
Bill Wendling
044b5344c4 Temporarily revert r68552. This was causing a failure in the self-hosting LLVM 
builds.

--- Reverse-merging (from foreign repository) r68552 into '.':
U    test/CodeGen/X86/tls8.ll
U    test/CodeGen/X86/tls10.ll
U    test/CodeGen/X86/tls2.ll
U    test/CodeGen/X86/tls6.ll
U    lib/Target/X86/X86Instr64bit.td
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86RegisterInfo.cpp
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86CodeEmitter.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86InstrInfo.h
U    lib/Target/X86/X86ISelDAGToDAG.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U    lib/Target/X86/X86ISelLowering.h
U    lib/Target/X86/X86InstrInfo.cpp
U    lib/Target/X86/X86InstrBuilder.h
U    lib/Target/X86/X86RegisterInfo.td



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-07 22:35:25 +00:00
Rafael Espindola
2a6411bbbd Reduce code duplication on the TLS implementation. 
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.

Will work on it and on X86-64 support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-07 21:37:46 +00:00
Evan Cheng
599a6a88ce Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-04 01:41:49 +00:00
Dan Gohman
d3f184906d Reformat the allocation-order arrays to a more conventional style. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63121 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 19:25:38 +00:00
Stuart Hastings
be362abe9c <rdar://problem/6351057> 
Discourage (allocate last) use of x86_64 R12 and R13 due to their
longer instruction encodings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59644 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-19 17:19:35 +00:00
Dale Johannesen
fb88f1f9a7 Remove unneeded stuff from GRAD register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59311 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-14 18:10:48 +00:00
Dale Johannesen
330169fa3e Extend InlineAsm::C_Register to allow multiple specific registers 
(actually, code already all worked, only the comment
changed).  Use this to implement 'A' constraint on x86.
Fixes PR 1779.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59266 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-13 21:52:36 +00:00
Evan Cheng
9ed08f4a41 Change x86 register allocation ordering to match that of gcc. Otherwise some tools get confused by prologue generated by llvm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58517 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 16:52:57 +00:00
Evan Cheng
ae270f66aa ATT asm printer just print register AsmName's instead of calling tolower on each charater of Name. This speeds it up by 10%. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53208 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-07 22:21:06 +00:00
Dale Johannesen
a68f9013f2 Add v2f32 (MMX) type to X86. Support is primitive: 
load,store,call,return,bitcast.  This is enough to
make call and return work.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52691 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-24 22:01:44 +00:00
Christopher Lamb
1fab4a6bbb Recommitting parts of r48130. These do not appear to cause the observed failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 10:09:17 +00:00
Evan Cheng
204496d58e In 32-bit mode, mark 64-bit GPR's as unallocatable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48217 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 07:16:00 +00:00
Chris Lattner
8e6da15e54 Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to 
copyfromreg/copytoreg instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48174 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 21:08:41 +00:00
Evan Cheng
4499e495ea Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 19:31:26 +00:00
Christopher Lamb
3feb0170a8 Allow insert_subreg into implicit, target-specific values. 
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 06:12:08 +00:00
Chris Lattner
8dc023f684 claim ST(x) registers are 80 bits, which is true. This doesn't affect 
codegen yet because these can't be spilled (they don't exist until after RA).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48098 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 07:49:01 +00:00
Dan Gohman
6f0d024a53 Rename MRegisterInfo to TargetRegisterInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-10 18:45:23 +00:00
Anton Korobeynikov
8eea339298 Provide correct DWARF register numbering for debug information emission on x86-32/Darwin. 
This should fix bunch of issues.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46337 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-25 00:34:13 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Anton Korobeynikov
f191c80cd7 Use TableGen to emit information for dwarf register numbers. 
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-11 19:50:10 +00:00
Dale Johannesen
7a42f24f0c Revert previous rewrite per chris's comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43950 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-09 18:07:11 +00:00
Dale Johannesen
3556bc1a9d Rewrite Dwarf number handling per review comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43918 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-09 00:47:10 +00:00
Dale Johannesen
4542edcaa7 Complete conditionalization of Dwarf reg numbers. 
Would somebody not on Darwin please make sure this
doesn't break anything.  Exception handling failures
would be the most likely symptom.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43844 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-07 21:48:35 +00:00
Arnold Schwaighofer
48abc5cf6b Corrected many typing errors. And removed 'nest' parameter handling 
for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 21:30:57 +00:00
Evan Cheng
dcfa73fe3c Set CCR (EFLAGS) copy cost to -1, i.e. extremely expensive to copy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42124 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-19 01:36:39 +00:00
Evan Cheng
3054dde813 Added status flags register: EFLAGS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41862 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 19:53:28 +00:00
Evan Cheng
a3231ba237 Temporarily backing out this change until we know why some dejagnu tests are failing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40973 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 22:25:35 +00:00
Evan Cheng
a333b41af9 GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40970 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 18:05:17 +00:00
Dale Johannesen
59a587337e Long double patch 4 of N: initial x87 implementation. 
Lots of problems yet but some simple things work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40847 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-05 18:49:15 +00:00