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1049 Commits

Author SHA1 Message Date
Eric Christopher
ec281c8934 Another possible bug. Stopgap until we can autogenerate tables and 
constraint lengths.

Part of rdar://9037836 and rdar://9119939



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132598 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 22:09:12 +00:00
Eric Christopher
ce1ecf59c8 Fix an off by one error. 
Part of rdar://9037836 and rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132590 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 20:44:52 +00:00
Eric Christopher
cf714d44b8 Make the Uv constraint a memory operand. This doesn't solve the 
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 17:24:37 +00:00
Eli Friedman
d6412c940e Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol. 
rdar://9431157



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 01:13:19 +00:00
Devang Patel
cf4cc84738 During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. 
Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132483 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 20:07:12 +00:00
Eric Christopher
9aaa02a1d2 Allow bitcasts between valid types of the same size and vector 
types if the vector type is legal.

Fixes rdar://9306086


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 19:55:10 +00:00
John McCall
5f8fd54f08 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

Take 2, now with more basic competence.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 19:50:32 +00:00
John McCall
7eebab2a82 I didn't mean to commit these residues of a personal project. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 19:41:56 +00:00
John McCall
832a9d1a76 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 19:39:04 +00:00
Bruno Cardoso Lopes
a0112d0c39 Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs 
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 04:07:29 +00:00
Eric Christopher
3c14f24c9d Implement the 'M' output modifier for arm inline asm. This is fairly 
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.

rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 01:40:44 +00:00
Cameron Zwarich
de64aaf6c8 Fix the remaining atomic intrinsics to use the right register classes on Thumb2, 
and add some basic tests for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 23:54:00 +00:00
Rafael Espindola
5b23b7fe31 Make size computation less brittle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132222 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 22:05:41 +00:00
Jakob Stoklund Olesen
484a718b55 Make room for register allocation to improve. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132213 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 20:15:06 +00:00
Evan Cheng
4abce0c90b Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 20:11:27 +00:00
Evan Cheng
d3444ff532 Add iOS test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 19:04:21 +00:00
Eli Friedman
45c4c4f257 And fix the test in r132194. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 18:14:28 +00:00
Eli Friedman
a4d487fc1e Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 18:02:04 +00:00
Devang Patel
785badb83e During branch folding avoid inserting redundant DBG_VALUE machine instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 21:47:59 +00:00
Eli Friedman
76927d7303 Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent. 
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 23:49:02 +00:00
Eric Christopher
8f89463894 Implement the 'm' modifier. Note that it only works for memory operands. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 20:51:58 +00:00
Cameron Zwarich
106acd4158 Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This 
fixes <rdar://problem/9495913>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:45:27 +00:00
Eric Christopher
4db7dec70b Implement the arm 'L' asm modifier. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 23:27:13 +00:00
Eric Christopher
e1739d598d Implement the immediate part of the 'B' modifier. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 23:15:43 +00:00
Eric Christopher
0628d38085 Add support for the arm 'y' asm modifier. 
Fixes part of rdar://9444657


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132011 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 22:10:34 +00:00
Cameron Zwarich
d34d429401 Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches 
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131894 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-23 01:57:17 +00:00
Renato Golin
1ec11fb8b5 RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131868 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-22 21:41:23 +00:00
Tanya Lattner
db28247522 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 21:44:54 +00:00
Tanya Lattner
2a8eb722c7 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 06:42:21 +00:00
Tanya Lattner
c81c9709ef vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 20:48:40 +00:00
Jakob Stoklund Olesen
f5497fb1b4 Teach LiveInterval::isZeroLength about null SlotIndexes. 
When instructions are deleted, they leave tombstone SlotIndex entries.
The isZeroLength method should ignore these null indexes.

This causes RABasic to sometimes spill a callee-saved register in the
abi-isel.ll test, so don't run that test with -regalloc=basic.  Prioritizing
register allocation according to spill weight can cause more registers to be
used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131436 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 23:50:05 +00:00
Galina Kistanova
60bf5c3197 Correction. Use explicit target triple in the test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-12 21:55:34 +00:00
Nadav Rotem
42febc6e99 Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain). 
If there is a store after the load node, then there is a chain, which means
that there is another user. Thus, asking hasOneUser would fail. Instead we
ask hasNUsesOfValue on the 'data' value.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131183 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 14:40:50 +00:00
Rafael Espindola
6253c7ca60 Produce a __debug_frame section on darwin ARM when appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 21:04:45 +00:00
Dan Gohman
becfb889aa Give this test an explicit register allocator, so that it can work even if 
the default register allocator is changed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130883 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 23:14:02 +00:00
Bill Wendling
d29052bf26 SjLj EH could produce a machine basic block that legitimately has more than one 
landing pad as its successor.

SjLj exception handling jumps to the correct landing pad via a switch statement
that's generated right before code-gen. Loosen the constraint in the machine
instruction verifier to allow for this. Note, this isn't the most rigorous check
since we cannot determine where that switch statement came from. But it's
marginally better than turning this check off when SjLj exceptions are used.
<rdar://problem/9187612>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130881 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 22:54:05 +00:00
Galina Kistanova
ff4f6eaf4e This test fails on ARM. The test shouldn't explicitly specify alignment (and alignment 4 is wrong) and requires hard-float. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130875 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 21:57:44 +00:00
Devang Patel
64915dec28 Do not emit location expression size twice. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130854 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 19:00:57 +00:00
Jakob Stoklund Olesen
feaf34758a Fix a bunch of ARM tests to be register allocation independent. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130800 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 22:31:21 +00:00
Evan Cheng
f35907f66b Make the test less likely to fail with minor changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130778 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 19:09:32 +00:00
Bob Wilson
22a751ac13 Remove test for iOS divmod function, since that is disabled for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130769 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:54:49 +00:00
Bruno Cardoso Lopes
54ad87ab78 Add a few ARM coprocessor intrinsics. Testcases included 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:29:22 +00:00
Dan Gohman
cca82149ad Add an unfolded offset field to LSR's Formula record. This is used to 
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 00:46:49 +00:00
Jakob Stoklund Olesen
d5b679c8ce Weekly fix of register allocation dependent unit tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-30 01:37:52 +00:00
Eli Friedman
b2b03fc2fa Make FastEmit_ri_ try a bit harder to succeed for supported operations; FastEmit_i can fail for non-Thumb2 ARM. Makes ARMSimplifyAddress work correctly, and reduces the number of fast-isel bailouts on non-Thumb ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 23:34:52 +00:00
Eli Friedman
c573e2c7ea Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 22:48:03 +00:00
Eli Friedman
51864a1d2b Fix run-line, again. :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130540 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 21:33:03 +00:00
Eli Friedman
9ebf57ae13 Re-committing r130454, which does not in fact break anything. 
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130539 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 21:22:56 +00:00
Eric Christopher
bcf26aee86 Add trunc->branch support, this won't help with clang's i8->i1 truncations 
for bools, but is a start.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130534 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 20:02:39 +00:00
Eli Friedman
6e6014cfb3 Revert r130454; apparently this doesn't actually work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130462 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 23:55:14 +00:00