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5103 Commits

Author SHA1 Message Date
Owen Anderson
b45b11bce1 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 22:00:41 +00:00
Jim Grosbach
c075510e43 Thumb2 t2Bcc should encode as t2B when condition is 'always'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138898 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:17:31 +00:00
Owen Anderson
721cb1fde0 Fix encoding for tBcc with immediate offset operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 20:26:14 +00:00
Owen Anderson
d84192fe4f When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. 
<rdar://problem/10046188>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 20:00:11 +00:00
Jim Grosbach
b80ab8e369 Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. 
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138879 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 18:39:39 +00:00
Owen Anderson
559c277aa9 Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138874 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 18:30:20 +00:00
Jim Grosbach
c9a9b44285 tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 18:29:05 +00:00
Jim Grosbach
72335d55d9 Thumb2 parsing and encoding for ADC(register). 
Also add instruction aliases for non-.w versions of SBC since they're the
same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 18:23:08 +00:00
Eli Friedman
4d3f329453 64-bit atomic cmpxchg for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 17:52:22 +00:00
Jim Grosbach
0f3abd8d68 Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 17:07:33 +00:00
Jakob Stoklund Olesen
6154582983 Put VMOVS widening under a command line option, off by default. 
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.

The failing test case is complicated, I am working on a reduction.

<rdar://problem/10044201>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 17:00:02 +00:00
Eli Friedman
3d93861c23 Some minor cleanups for r138845. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 00:41:05 +00:00
Eli Friedman
2bdffe4882 Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 00:31:29 +00:00
Owen Anderson
eaca928a37 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 22:58:27 +00:00
Owen Anderson
21df36c57a Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 22:15:17 +00:00
Owen Anderson
a7710edd98 Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138835 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 22:10:03 +00:00
Owen Anderson
391ac65377 Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138834 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 22:03:20 +00:00
Owen Anderson
10096dbdef Clean up whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 21:58:18 +00:00
Evan Cheng
37fefc20d3 Follow up to r138791. 
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 19:09:48 +00:00
Evan Cheng
342e3161d9 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 01:34:54 +00:00
Jim Grosbach
d3765189bf Revert 138781. It's not playing nicely with the immediate forms for ADC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138782 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 23:24:15 +00:00
Jim Grosbach
e94a5b1218 Thumb2 assembler aliases for ADC/SBC w/o the .w suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 23:20:54 +00:00
Owen Anderson
694e0ffb8a Add missing encoding information for some of the GPR<->FP register moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 23:15:25 +00:00
Jim Grosbach
f8e1e3e729 Thumb2 parsing and encoding for IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 22:24:09 +00:00
Owen Anderson
acb274baac Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 21:14:19 +00:00
Owen Anderson
1f26758510 Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138760 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 20:42:00 +00:00
Owen Anderson
c4e16de765 addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138758 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 20:16:50 +00:00
Owen Anderson
0da10cf44d Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 19:36:44 +00:00
Eli Friedman
4db5acaf48 Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 18:23:02 +00:00
Owen Anderson
07700d486e Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 17:59:41 +00:00
Owen Anderson
63553c77cd Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 17:17:09 +00:00
Benjamin Kramer
2753ae314f Silence GCC warnings and make an array const. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138706 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-27 17:36:14 +00:00
Owen Anderson
f1eab597b2 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 23:32:08 +00:00
Owen Anderson
d7568e1c35 Correct encoding of BL with immediate offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 22:54:51 +00:00
Jim Grosbach
4af54a461f ARM assembly parsing tweak for pldw. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 22:21:51 +00:00
Owen Anderson
9f7e831994 Spelling fail. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138667 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:47:57 +00:00
Jim Grosbach
89df996ab2 Thumb2 assembler parsing and encoding of IT instruction. 
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138665 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:43:41 +00:00
Owen Anderson
2b568fb3ce Fix ARM codegen breakage caused by r138653. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138657 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:12:37 +00:00
Owen Anderson
9ab0f25fc1 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 20:43:14 +00:00
Owen Anderson
1af7f7291d Update for feedback from Jim. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 19:39:26 +00:00
Benjamin Kramer
86ce852a15 ARMDisassembler: Always return a size, even when disassembling fails. 
This should fix PR10772.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 18:21:36 +00:00
Owen Anderson
96425c8464 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 18:09:22 +00:00
Owen Anderson
9bd655dcde Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. 
This is the last disassembly crash detected by exhaustive Thumb2 instruction space.  Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 06:19:51 +00:00
Eli Friedman
069e2ed794 Atomic load/store on ARM/Thumb. 
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 02:59:24 +00:00
Nick Lewycky
b210cbf692 Remove stray fullstop. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138589 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 21:46:20 +00:00
Owen Anderson
99906830e8 Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 18:30:18 +00:00
Andrew Trick
b9ca5124f8 ARM fix for missing implicit operands on ldmia_ret. 
rdar://10005094: miscompile of 176.gcc


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138568 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 17:50:53 +00:00
Andrew Trick
51972da576 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 17:40:54 +00:00
Jim Grosbach
0c49ac05cd Explicitly disallow predication in Thumb1 assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138562 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 17:23:55 +00:00
Evan Cheng
77eaaf0a0c Hide -global-merge option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138540 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 01:22:49 +00:00