Commit Graph

30 Commits

Author SHA1 Message Date
Chris Lattner
b5d01436e3 Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24595 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 02:34:29 +00:00
Duraid Madina
889649e78e add FP select. next up - divide!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24346 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-14 01:17:30 +00:00
Duraid Madina
49fcc4006c fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24175 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-04 00:57:56 +00:00
Duraid Madina
0e5e0d14a8 add pattern to load constant 0 into a predicate reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24164 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-03 10:09:32 +00:00
Chris Lattner
61bc60fc4f Fix a bug that prevented this pattern from matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24161 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-03 05:45:34 +00:00
Chris Lattner
cb2583e17d This works now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24150 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-02 06:49:37 +00:00
Duraid Madina
5966955445 add support for SELECT to TargetSelectionDAG.td, add support for
selecting ints to IA64, and a few other ia64 bits and pieces


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24147 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-02 02:37:18 +00:00
Duraid Madina
aba8457125 so tablegen was thinking I might want to convert FPs to predicates.
clever little tablegen!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24133 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-01 03:32:15 +00:00
Duraid Madina
e2fd9e2d9d add support for int->FP and FP->int ops, and add ia64 patterns for these
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24132 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-01 03:07:25 +00:00
Duraid Madina
d1eda6d155 add zeroextend predicate->integer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24131 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-01 01:29:55 +00:00
Duraid Madina
363aff2f3c add FP compares and implicit register defs to the dag isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24118 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-31 01:42:11 +00:00
Duraid Madina
5c2c64e567 fix some broken comparisons, this affected the Pattern isel too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24109 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 10:14:19 +00:00
Duraid Madina
25d0a88eb8 add some FP stuff, some mix.* stuff, and constant pool support to the
DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24094 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-29 16:08:30 +00:00
Duraid Madina
274ecfb782 add shladd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24080 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-29 04:13:40 +00:00
Duraid Madina
f2db9b88da DAG->DAG instruction selection for ia64! "hello world" works, not much else.
use -enable-ia64-dag-isel to turn this on

TODO: delete lowering stuff from the pattern isel
    : get operations on predicate bits working
    : get other bits of pseudocode going
    : use sampo's mulh/mull-using divide-by-constant magic
    : *so* many patterns ("extr", "tbit" and "dep" will be fun :)
    : add FP
    : add a JIT!
    : get it working 100%

in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.

OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24058 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-28 17:46:35 +00:00
Chris Lattner
2e3f5db9ff Give all operands names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23357 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-14 21:11:13 +00:00
Chris Lattner
efc58be8ca Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR.
I'm not convinced this is all of them,  but I can't do much testing, because
IA64 LLC crashes on big programs :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22892 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 00:47:42 +00:00
Duraid Madina
63bbed536c add the popcount instruction and support this in the isel
the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21860 91177308-0d34-0410-b5e6-96231b3b80d8
2005-05-11 05:16:09 +00:00
Duraid Madina
1ce0c015ad print negative 64 bit immediates as negative numbers, makes things a little
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21300 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14 10:08:01 +00:00
Duraid Madina
ed09502a0b * add the shladd instruction
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21282 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13 06:12:04 +00:00
Chris Lattner
ea6f770fb0 Make sure to realize that calls use their argument regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21248 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12 15:12:19 +00:00
Duraid Madina
5ef2ec9929 assorted fixes:
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
  * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
  * fix nasty thinko - didn't use two-address form of conditional add
    for extending bools to integers, so occasionally there would be
    garbage in the result. it's amazing how often zeros are just
    sitting around in registers ;) - this should fix a bunch of tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21221 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11 05:55:56 +00:00
Duraid Madina
6dcceb5ecb fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn)
fix hack in division (clean up frcpa instruction)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21153 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-08 10:01:48 +00:00
Duraid Madina
18c0c6bcc4 add immediate forms of add, sub, shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21129 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-07 12:32:24 +00:00
Duraid Madina
b366a02ff2 add fms instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21112 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 09:54:09 +00:00
Duraid Madina
09c61b9c19 add implicit use op
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21074 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 04:50:57 +00:00
Duraid Madina
5c156b7473 add fnegabs op
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21022 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 10:06:27 +00:00
Duraid Madina
a7ee8b8f04 add support FNEG and FABS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21012 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 05:18:38 +00:00
Duraid Madina
291e1266c1 add what we need to fudge a 'floating point conditional move', this is
used to get FP div-by-zero working properly (shunt the right answer
depending on how frcpa sets its predicate output)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20954 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-31 07:32:32 +00:00
Duraid Madina
9b9d45f60e and so it begins...
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20652 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-17 18:17:03 +00:00