Commit Graph

103594 Commits

Author SHA1 Message Date
Daniel Sanders
b6569388b9 [mips] Marked up instructions added in MIPS32 and tested that IAS for -mcpu=mips2 does not accept them
Summary:
To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are explicitly tested.

Depends on D3695

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3696

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208549 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 13:04:32 +00:00
Rafael Espindola
7b6f59e8f6 Remove MCUseCFI from TargetMachine.
It was always true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208547 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 13:01:42 +00:00
Daniel Sanders
31546cd352 [mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-V that was available in MIPS32R2

Most of these instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now. It happens
because many of the MIPS V instructions have not been implemented.

Depends on D3694

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208546 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:52:44 +00:00
Daniel Sanders
b396af3752 [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64
Summary:
DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no
effect on the CodeGen tests since expansion of i64 prevented their use
anyway.

The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as
well. This is not a functional change since DCLZ is still prohibited by
being a MIPS64 instruction (MIPS16 is only compatible with MIPS32).

No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3694

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208544 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:41:59 +00:00
Daniel Sanders
ea27d2f50b [mips] Fold FeatureSEInReg into FeatureMips32r2
Summary: No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3693

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208543 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:28:15 +00:00
Daniel Sanders
d46b2e219d [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2
Summary:
dsbh and dshd are not available on Mips32r2. No codegen test changes
required since expansion of i64 prevented the use of these instructions
anyway.

Depends on D3690

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208542 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:15:41 +00:00
Daniel Sanders
4119c5f9f4 [mips] Replace FeatureFPIdx with FeatureMips4_32r2
Summary:
No functional change.

The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions)

Depends on D3677

Reviewers: rkotler, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3690

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208541 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 11:56:16 +00:00
Bradley Smith
b0b587163d [ARM64] Add proper bounds checking/diagnostics to logical shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208540 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 11:49:16 +00:00
Christian Pirker
5c39a97a60 ARM: Implement big endian bit-conversion for NEON type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208538 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 11:19:20 +00:00
NAKAMURA Takumi
7aa3041087 X86ISelLowering.cpp:LowerINTRINSIC_W_CHAIN(): Prune impossible "default:" [-Wcovered-switch-default]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208533 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 10:16:46 +00:00
Serge Pavlov
b1a6b91a1e Fix type of shuffle obtained from reordering with binary operation
In transformation:
    BinOp(shuffle(v1,undef), shuffle(v2,undef)) -> shuffle(BinOp(v1, v2),undef)
type of the undef argument must be same as type of BinOp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208531 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 10:11:27 +00:00
Bradley Smith
f1e04540f6 [ARM64] Add diagnostics for bitfield extract/insert instructions
Unfortunately, since ARM64 models all these instructions as aliases,
the checks need to be done at the time the alias is seen rather than
during instruction validation as AArch64 does it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 09:44:57 +00:00
Bradley Smith
0ce7616654 [ARM64] Correct more bounds checks/diagnostics for arithmetic shift operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 09:41:43 +00:00
Bradley Smith
0d919c62c4 [ARM64] Move register/register MOV handling into tablegen and improve diagnostics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208527 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 09:38:16 +00:00
Elena Demikhovsky
e7dd13a094 Fixed compilation issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 07:45:41 +00:00
Elena Demikhovsky
1cec507d6d AVX-512: changes in intrinsics
1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed.
2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012).
3) I added gather/scatter prefetch intrinsics.
4) I fixed MRMm encoding for masked instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 07:18:51 +00:00
Saleem Abdulrasool
f37d8e6b1a CodeGen: add parenthesis around complex expression
Add missing parenthesis suggested by GCC.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208519 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 06:08:18 +00:00
Serge Pavlov
0795830269 Fix reordering of shuffles and binary operations
Do not apply transformation:

    BinOp(shuffle(v1), shuffle(v2)) -> shuffle(BinOp(v1, v2))

if operands v1 and v2 are of different size.
This change fixes PR19717, which was caused by r208488.
    


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208518 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 05:44:53 +00:00
NAKAMURA Takumi
8b6f7428b0 Reformat blank lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 03:32:56 +00:00
Matt Arsenault
d0c1b54942 Fix return before else
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208510 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 21:24:41 +00:00
Hal Finkel
70a83b490e [PowerPC] Add global named register support
Support for the intrinsics that read from and write to global named registers
is added for r1, r2 and r13 (depending on the subtarget).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208509 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 19:29:11 +00:00
Hal Finkel
24f554f052 Pass the value type to TLI::getRegisterByName
We must validate the value type in TLI::getRegisterByName, because if we
don't and the wrong type was used with the IR intrinsic, then we'll assert
(because we won't be able to find a valid register class with which to
construct the requested copy operation). For PPC64, additionally, the type
information is necessary to decide between the 64-bit register and the 32-bit
subregister.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208508 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 19:29:07 +00:00
Hal Finkel
94a03fcf38 Add 'override' to getRegisterByName in *ISelLowering.h
No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208507 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 19:28:55 +00:00
David Blaikie
99ccb1fae7 DebugInfo: Include lexical scopes in inlined subroutines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208506 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 18:12:17 +00:00
David Blaikie
db692e7d55 DebugInfo: Simplify/correct test for correct constant emission when dealing with derived types.
This test was using the inliner and other optimizations to test a case
that's actually a bug anyway. Bug and possible fix/discussion described
here ( http://reviews.llvm.org/D3714 ).

But the functionality that was implemented along with this test is still
desired, so simplify the test to verify a more obvious/less wrong case
that the functionality addressed: looking through const sugar to the
underlying type when emitting a constant (so the constant is emitted as
signed/unsigned as appropriate depending on the signedness of the
underlying type).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208504 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 17:25:50 +00:00
David Blaikie
42e3b31d69 DwarfUnit: Make explicit a limitation/bug in enumeration constant emission.
Filed as PR19712, LLVM fails to detect the right type of an enum
constant when a frontend does not provide an underlying type for the
enumeration type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208502 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 17:04:05 +00:00
Hal Finkel
87f4cf7028 [PowerPC] On PPC32, 128-bit shifts might be runtime calls
The counter-loops formation pass needs to know what operations might be
function calls (because they can't appear in counter-based loops). On PPC32,
128-bit shifts might be runtime calls (even though you can't use __int128 on
PPC32, it seems that SROA might form them).

Fixes PR19709.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208501 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 16:23:29 +00:00
David Blaikie
f2bd335042 DwarfUnit: Pick a winner between isTypeSigned and isUnsignedDIType.
And the winner by a nose is isUnsignedDIType, for no particular reason.

These two functions were just complements of each other and used in very
related code, so refactor callers to just use one of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208500 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 16:08:41 +00:00
David Blaikie
9cfc5b23a1 DwarfUnit: Factor out calling isUnsignedDIType into a utility function so each caller of emitConstantValue doesn't have to call it separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 15:56:59 +00:00
David Blaikie
abfe7d33c7 DwarfUnit: Share common constant value emission between APInts of small (<= 64 bit) and MCOperand immediates.
Doesn't seem a good reason to duplicate this code (it was more literally
duplicated prior to r208494, and while the dataN code /does/ actually
fire in this case, it doesn't seem necessary (and the DWARF standard
recommends using udata/sdata pervasively instead of dataN, so as to
indicate signedness of the values))

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208495 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 15:47:39 +00:00
David Blaikie
d0125ee381 DebugInfo: Simplify constant value emission.
This code looks to have become dead at some time in the past. I tried to
reproduce cases where LLVM would emit constants with dataN, but could
not. Upon inspection it seems the code doesn't do that anymore - the
only time a size is provided by isTypeSigned is when the type is signed,
and in those cases we use sdata. dataN is only used for unsigned types
and isTypeSigned doesn't provide a value for sizeInBits in that case.

Remove the dead cases/size plumbing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208494 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 15:06:20 +00:00
Benjamin Kramer
4db3f41012 SLPVectorizer: Instead of just performing CSE on dead blocks ignore them completely.
Turns out that there is a very cheap way of testing whether a block is dead,
just look it up in the DomTree. We have to do this anyways so just ignore
unreachable blocks before sorting by domination. This restores a proper
ordering for std::stable_sort when dead code is present.

Covered by existing tests & buildbots running in STL debug mode (MSVC).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208492 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 10:28:58 +00:00
Simon Atanasyan
f5e04c38cd [llvm-readobj] Print values of FLAGS and MIPS_FLAGS dynamic table tags
in a human readable form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208489 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 08:48:09 +00:00
Serge Pavlov
86118b4532 Reorder shuffle and binary operation.
This patch enables transformations:

    BinOp(shuffle(v1), shuffle(v2)) -> shuffle(BinOp(v1, v2))
    BinOp(shuffle(v1), const1) -> shuffle(BinOp, const2)

They allow to eliminate extra shuffles in some cases.

Differential Revision: http://reviews.llvm.org/D3525


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208488 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 08:46:12 +00:00
Filipe Cabecinhas
4ccf0ebb19 Fixed a bug when lowering build_vector (PR19694)
When lowering build_vector to an insertps, we would still lower it, even
if the source vectors weren't v4x32. This would break on avx if the source
was a v8x32. We now check the type of the source vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208487 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 08:12:56 +00:00
Vincent Lejeune
e283f74133 R600/SI: Fold fabs/fneg into src input modifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208480 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 19:18:39 +00:00
Vincent Lejeune
3378ca7d5c R600/SI: Prettier display of input modifiers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 19:18:33 +00:00
Vincent Lejeune
d19e830174 R600/SI: Use pseudo instruction for fabs/clamp/fneg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 19:18:25 +00:00
Benjamin Kramer
bfd5dad4c9 SCEV: Use range-based for loop and fold variable into assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 17:47:18 +00:00
Tim Northover
e87cadc49a ARM64: fix SELECT_CC lowering in absence of NaNs.
We were swapping the true & false results while testing for FMAX/FMIN,
but not putting them back to the original state if the later checks
failed.

Should fix PR19700.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208469 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 07:37:50 +00:00
Kevin Enderby
ae417592a5 Fix llvm-nm to print the full 64-bit address for symbols in 64-bit object files.
The implementation might be better to have a method is64Bit() in the class
SymbolicFile instead of having the static routine isSymbolList64Bit() in
llvm-nm.cpp .  But this is very much in the sprit of isObject() and
getNMTypeChar() in llvm-nm.cpp that has a series of if else statements
based on the specific class of the SymbolicFile.  I can update this if
folks would like.

Also the tests were updated to be explicit about checking the address for
64-bits or 32-bits from object files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 23:57:49 +00:00
Benjamin Kramer
3ae331d81a SLPVectorizer: When sorting by domination for CSE don't assert on unreachable code.
There is no total ordering if the CFG is disconnected. We don't care if we
catch all CSE opportunities in dead code either so just exclude ignore them in
the assert.

PR19646

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208461 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 23:28:49 +00:00
Reid Kleckner
d30c11edde Revert "[ms-cxxabi] Add a new calling convention that swaps 'this' and 'sret'"
This reverts commit r200561.

This calling convention was an attempt to match the MSVC C++ ABI for
methods that return structures by value.  This solution didn't scale,
because it would have required splitting every CC available on Windows
into two: one for methods and one for free functions.

Now that we can put sret on the second arg (r208453), and Clang does
that (r208458), revert this hack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208459 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 22:56:42 +00:00
Sebastian Pop
754e940865 move findArrayDimensions to ScalarEvolution
we do not use the information from SCEVAddRecExpr to compute the shape of the array,
so a better place for this function is in ScalarEvolution.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208456 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 22:45:07 +00:00
Sebastian Pop
f255eb9643 fix typo in debug message
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208455 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 22:45:02 +00:00
Reid Kleckner
805a83c041 Allow sret on the second parameter as well as the first
MSVC always places the implicit sret parameter after the implicit this
parameter of instance methods.  We used to handle this for
x86_thiscallcc by allocating the sret parameter on the stack and leaving
the this pointer in ecx, but that doesn't handle alternative calling
conventions like cdecl, stdcall, fastcall, or the win64 convention.

Instead, change the verifier to allow sret on the second parameter.

This also requires changing the Mips and X86 backends to return the
argument with the sret parameter, instead of assuming that the sret
parameter comes first.

The Sparc backend also returns sret parameters in a register, but I
wasn't able to update it to handle secondary sret parameters.  It
currently calls report_fatal_error if you feed it an sret in the second
parameter.

Reviewers: rafael.espindola, majnemer

Differential Revision: http://reviews.llvm.org/D3617

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208453 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 22:32:13 +00:00
Reid Kleckner
b3275b9fca Fix ARM intrinsics-overflow.ll test on Windows
Windows on ARM only supports thumb mode execution, so we have to
explicitly pick some non-Windows OS to test ARM mode codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208448 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 21:52:48 +00:00
Rafael Espindola
1acea2db56 Don't crash on redefinitions.
One error we were not deleting the alias or putting it in the Module. The
end result is that there was an use left of the aliasee when the module was
deleted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208447 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 21:49:17 +00:00
Jonathan Roelofs
482018007c Fix broken build
ARM64 backend was missing a required_library entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 18:06:22 +00:00
Louis Gerbarg
7a9fbab182 Add custom lowering for add/sub with overflow intrinsics to ARM
This patch adds support to ARM for custom lowering of the
llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful
for handling idiomatic saturating math functions as generated by
InstCombineCompare.

Test cases included.

rdar://14853450

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208435 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 17:02:49 +00:00