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b7880ac470
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9439 Commits

Author SHA1 Message Date
Evan Cheng
b7880ac470 Addr1 instructions opcodes are encoded in bits 21-24; encode S bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55590 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 18:32:16 +00:00
Gabor Greif
93c53e5583 fix a bunch of 80-col violations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55588 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 15:37:04 +00:00
Bill Wendling
9440e35b98 Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR 
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55582 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 02:59:23 +00:00
Bill Wendling
3156b62855 Expand for ROTR with MVT::i64. 
Dale, Could you please review this?


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55581 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 02:53:19 +00:00
Gabor Greif
92362680c1 fix some 80-col violations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55565 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 10:09:02 +00:00
Evan Cheng
b18ae3cb63 For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55562 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 08:54:22 +00:00
Evan Cheng
eb9f89287e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 02:03:58 +00:00
Dale Johannesen
ea9eedb787 Add ppc partial-word ATOMIC_CMP_SWAP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55554 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 00:08:53 +00:00
Evan Cheng
456704476f Swap fp comparison operands and change predicate to allow load folding (safely this time). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55553 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 23:22:12 +00:00
Evan Cheng
97af60b3ae Use static_cast instead of C style cast. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55552 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 23:21:31 +00:00
Evan Cheng
94a50da93c Backing out 55521. Not safe. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55548 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 22:13:21 +00:00
Dale Johannesen
0e55f0678c Add partial word version of ATOMIC_SWAP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55546 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 18:29:46 +00:00
Owen Anderson
667d8f7607 Add initial support for fast isel of instructions that have inputs pinned to physical registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55545 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 17:45:56 +00:00
Evan Cheng
ba705f62b1 TableGen'ing instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 07:42:03 +00:00
Evan Cheng
612b79edc9 addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 07:40:52 +00:00
Evan Cheng
3924f78a96 MVN is addrmode1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55530 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 07:36:24 +00:00
Evan Cheng
130966411f More refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 06:41:12 +00:00
Evan Cheng
4d46d0af58 Swap fp comparison operands and change predicate to allow load folding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:48:31 +00:00
Evan Cheng
37f25d989a Refactor ARM instruction format definitions into a separate file. No functionality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:39:26 +00:00
Dan Gohman
99b218218c Add a target callback for FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:21:34 +00:00
Gabor Greif
327ef031ed remove tabs, fix > 80 cols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55511 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:19:51 +00:00
Gabor Greif
ba36cb5242 erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 21:40:38 +00:00
Mon P Wang
5ad0bf658a In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55499 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 21:04:05 +00:00
Rafael Espindola
833a990c26 Use resize instead of reserve. Reserve doesn't change size(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55486 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 18:32:53 +00:00
Dale Johannesen
97efa36586 Implement partial-word binary atomics on ppc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55478 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 17:53:09 +00:00
Evan Cheng
66e13153bd FsFLD0S{S|D} and V_SETALLONES are as cheap as moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55466 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 07:52:25 +00:00
Dale Johannesen
e00a8a2a2e Split the ATOMIC NodeType's to include the size, e.g. 
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 02:44:49 +00:00
Bill Wendling
1dd0086b06 Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the 
SSE2 registers as well as the MMX registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55436 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 21:32:04 +00:00
Dan Gohman
7deb17108f Reinstate the x86-64 portion of r55190. When doing extloads into 
64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55422 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 17:33:15 +00:00
Gabor Greif
99a6cb92d1 disallow direct access to SDValue::ResNo, provide a getter instead 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 22:36:50 +00:00
Owen Anderson
a317767f0e These assertions should be return false's instead, allowing the client to detect the failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55377 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 18:50:40 +00:00
Owen Anderson
940f83e772 Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested 
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 18:03:31 +00:00
Chris Lattner
6ba50a9252 If an xmm register is referenced explicitly in an inline asm, make sure to 
assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55358 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 06:19:02 +00:00
Evan Cheng
b09c25ebf0 This is done. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55348 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 01:13:44 +00:00
Dale Johannesen
bdab93a2ef Implement 32 & 64 bit versions of PPC atomic 
binary primitives.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55343 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 22:34:37 +00:00
Evan Cheng
bdf7b5da47 80 col. violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55341 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 21:58:43 +00:00
Evan Cheng
ab6c3bb44d Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55338 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 21:27:18 +00:00
Dale Johannesen
140a8bb006 Remove PPC-specific lowering for atomics; the 
generic stuff works fine.

Mark rewritten cmp-and-swap as not using CR1.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55336 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 21:09:52 +00:00
Dale Johannesen
65e3973dff It's important for the cmp-and-swap to balance 
loads and stores but it's even more important for
it to store the right value.:(



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55319 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 18:53:26 +00:00
Bill Wendling
cb3c51a4ae Nevermind. This broke the bootstrap (?!). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55318 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 18:32:39 +00:00
Bill Wendling
51e05e7a99 MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these 
instructions on having SSE2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55317 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 18:20:52 +00:00
Evan Cheng
e7321441ac Fix asm printing of MOVSDto64mr and MOV64toSDrm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55300 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 04:11:42 +00:00
Bill Wendling
59b63e4a18 Temporarily reverting r55292. It's causing a bootstraping failure: 
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55295 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-24 21:45:30 +00:00
Evan Cheng
32c727cd95 Move callseq_start above the call address load to allow load to be folded into the call node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55292 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-24 19:19:55 +00:00
Cedric Venet
d85f51abd4 Use additionnal include directory instead of ../ in #include. 
Suggested by aKor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55282 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-24 12:30:46 +00:00
Chris Lattner
944fac71e0 Switch the asmprinter (.ll) and all the stuff it requires over to 
use raw_ostream instead of std::ostream.  Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).

Other interesting changes:
 1) This makes Value::print be non-virtual.
 2) AP[S]Int and ConstantRange can no longer print to ostream directly, 
    use raw_ostream instead.
 3) This fixes a bug in raw_os_ostream where it didn't flush itself 
    when destroyed.
 4) This adds a new SDNode::print method, instead of only allowing "dump".


A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream 
versions.

This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55263 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-23 22:23:09 +00:00
Anton Korobeynikov
017c260944 Provide a 64 bit variant of mmx.maskmovq intrinsic lowering. 
Is there way to avoid explicit target check?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55238 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-23 15:53:19 +00:00
Dan Gohman
f350b277f3 Move the point at which FastISel taps into the SelectionDAGISel 
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-23 02:25:05 +00:00
Anton Korobeynikov
70f24c62ad Make option variables static, so they won't cause nameclash 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55203 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 21:27:49 +00:00
Bill Wendling
449416deb6 Reverting r55190, r55191, and r55192. They broke the build with this error message: 
{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55200 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 20:51:05 +00:00