Commit Graph

19034 Commits

Author SHA1 Message Date
Alex Lorenz b82063e6e5 MIR Parser: Extract the method 'parseGlobalValue'. NFC.
This commit extracts the code that parses a global value from the method
'parseGlobalAddressOperand' into a new method 'parseGlobalValue', so that this
code can be reused by the method which will parse the block address machine
operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243450 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 17:09:52 +00:00
Alex Lorenz e787364571 MIR Parser: Move the function 'lexName'. NFC.
This commit moves the function 'lexName' to the start of the file so it can
be reused by the function which will lex the named LLVM IR block references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243449 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 17:03:40 +00:00
Alex Lorenz 8302e12df3 MIR Printer: Remove an outdated TODO comment and assertion. NFC.
This commit removes an outdated TODO comment and a corresponding assertion
which asserts that the mir printer can't the print machine basic blocks that
aren't sequentially numbered.

This comment and assertion were correct when I was working on the patch which
serialized the machine basic blocks, but then I decided to add an 'ID'
attribute to the machine basic block's YAML mapping based on the patch review.
This comment and assertion then became invalid as with the 'ID' attribute we
can serialize the non sequential machine basic blocks and their references
without any problems.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243447 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 16:56:45 +00:00
Alex Lorenz 3e85c48d36 MIR Parser: Remove redundant parameters. NFC.
This commit removes the redundant parameters from the two methods
'initializeRegisterInfo' and 'initializeFrameInfo'. The removed parameters are
redundant as we are already passing in the 'MachineFunction' to those methods,
and those parameters can be derived from the machine function parameter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243445 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 16:48:37 +00:00
Chih-Hung Hsieh dc73dc09f1 Implement target independent TLS compatible with glibc's emutls.c.
The 'common' section TLS is not implemented.
Current C/C++ TLS variables are not placed in common section.
DWARF debug info to get the address of TLS variables is not generated yet.

clang and driver changes in http://reviews.llvm.org/D10524

  Added -femulated-tls flag to select the emulated TLS model,
  which will be used for old targets like Android that do not
  support ELF TLS models.

Added TargetLowering::LowerToTLSEmulatedModel as a target-independent
function to convert a SDNode of TLS variable address to a function call
to __emutls_get_address.

Added into lib/Target/*/*ISelLowering.cpp to call LowerToTLSEmulatedModel
for TLSModel::Emulated. Although all targets supporting ELF TLS models are
enhanced, emulated TLS model has been tested only for Android ELF targets.
Modified AsmPrinter.cpp to print the emutls_v.* and emutls_t.* variables for
emulated TLS variables.
Modified DwarfCompileUnit.cpp to skip some DIE for emulated TLS variabls.

TODO: Add proper DIE for emulated TLS variables.
      Added new unit tests with emulated TLS.

Differential Revision: http://reviews.llvm.org/D10522


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243438 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 16:24:05 +00:00
Puyan Lotfi fbb4b5254d Changes for MachineBasicBlock to use SortedVector for LiveIns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243389 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 06:38:41 +00:00
Mehdi Amini 3942a2979d Move the Target way of overriding DAG Scheduler to a target hook
Summary:
The previous way of overriding it was relying on calling "setDefault"
on the global registry, which implies global mutable state.

Reviewers: echristo, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11538

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243388 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 06:18:04 +00:00
Alex Lorenz 01b5d5b27f MIR Serialization: Serialize the unnamed basic block references.
This commit serializes the references from the machine basic blocks to the
unnamed basic blocks.

This commit adds a new attribute to the machine basic block's YAML mapping
called 'ir-block'. This attribute contains the actual reference to the
basic block.

Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243340 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 22:42:41 +00:00
Alex Lorenz 1c1ccc2527 MIR Serialization: Serialize the '.cfi_def_cfa_register' CFI instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243322 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 20:39:03 +00:00
Alex Lorenz 342851440d MIR Parser: Rename the standalone parsing methods. NFC.
This commit renames the methods 'parseMBB' and 'parseNamedRegister' to
'parseStandaloneMBB' and 'parseStandaloneNamedRegister' in order for their
names to be consistent with the method 'parseStandaloneVirtualRegister'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243319 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 20:29:27 +00:00
Bruno Cardoso Lopes 272154cc86 Revert "[PeepholeOptimizer] Look through PHIs to find additional register sources"
Still breaks some ARM buildbots. This reverts r243271.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243318 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 20:26:04 +00:00
Sanjay Patel 5834764c65 move combineRepeatedFPDivisors logic into a helper function; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243293 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 17:58:49 +00:00
Alex Lorenz 6c304ebd8a Reset the virtual registers in liveins when clearing the virtual registers.
This commit zeroes out the virtual register references in the machine
function's liveins in the class 'MachineRegisterInfo' when the virtual
register definitions are cleared.

Reviewers: Matthias Braun


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243290 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 17:51:59 +00:00
Alex Lorenz a5da4f1f8d MIR Serialization: Serialize the machine function's liveins.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243288 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 17:42:45 +00:00
Bruno Cardoso Lopes 4abd22ba6b [PeepholeOptimizer] Look through PHIs to find additional register sources
Reapply r242295 with fixes in the implementation.

- Teaches the ValueTracker in the PeepholeOptimizer to look through PHI
instructions.
- Add findNextSourceAndRewritePHI method to lookup into multiple sources
returnted by the ValueTracker and rewrite PHIs with new sources.

With these changes we can find more register sources and rewrite more
copies to allow coaslescing of bitcast instructions. Hence, we eliminate
unnecessary VR64 <-> GR64 copies in x86, but it could be extended to
other archs by marking "isBitcast" on target specific instructions. The
x86 example follows:

A:
  psllq %mm1, %mm0
  movd  %mm0, %r9
  jmp C

B:
  por %mm1, %mm0
  movd  %mm0, %r9
  jmp C

C:
  movd  %r9, %mm0
  pshufw  $238, %mm0, %mm0

Becomes:

A:
  psllq %mm1, %mm0
  jmp C

B:
  por %mm1, %mm0
  jmp C

C:
  pshufw  $238, %mm0, %mm0

Differential Revision: http://reviews.llvm.org/D11197
rdar://problem/20404526

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243271 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 14:39:46 +00:00
Alex Lorenz 3a8b87d9ce MIR Serialization: Serialize MachineFrameInfo's callee saved information.
This commit serializes the callee saved information from the class
'MachineFrameInfo'. This commit extends the YAML mappings for the fixed and
the ordinary stack objects and adds an optional 'callee-saved-register'
attribute. This attribute is used to serialize the callee save information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243173 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 22:22:50 +00:00
Pete Cooper 9f2f1650c4 Use make_range(rbegin(), rend()) to allow foreach loops. NFC.
Instead of the pattern

for (auto I = x.rbegin(), E = x.end(); I != E; ++I)

we can use make_range to construct the reverse range and iterate using
that instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243163 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 21:13:43 +00:00
Duncan P. N. Exon Smith 88c307a010 AsmPrinter: Use DICompositeType in updateAcceleratorTables(), NFC
`DISubroutineType` is impossible at this `dyn_cast` site, since we're
only dealing with named types and `DISubroutineType` cannot be named.
Strengthen the `dyn_cast` to `DICompositeType`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243157 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 20:45:26 +00:00
Alex Lorenz dfe0e536ee MIR Serialization: Serialize the simple virtual register allocation hints.
This commit serializes the virtual register allocations hints of type 0.
These hints specify the preferred physical registers for allocations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243156 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 20:35:40 +00:00
Duncan P. N. Exon Smith 18673740dc DI: Clarify isUnsignedDIType(), NFC
Refactor `isUnsignedDIType()` to deal with `DICompositeType` explicitly.
Since `DW_TAG_subroutine_type` isn't handled here (the assertions about
tags rule it out), this allows strengthening the `dyn_cast` to
`DIDerivedType`.

Besides making the code clearer, this it removes a use of
`DIDerivedTypeBase`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243148 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 19:42:12 +00:00
Duncan P. N. Exon Smith e4a9f1b6e7 DI: Strengthen block-byref cast to DIDerivedType, NFC
This code is visiting the members of a block-byref, and we know those
are all `DIDerivedType`.  Strengthen the cast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243138 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 18:58:32 +00:00
Duncan P. N. Exon Smith a012f0dcc4 DI: Only DICompositeType has getElements(), NFC
There is an assertion inside `DICompositeTypeBase::getElements()` that
`this` is not a `DISubroutineType`, leaving only `DICompositeType`.
Make that clear at the call sites.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243134 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 18:17:17 +00:00
Alex Lorenz 56cf65b377 MIR Parser: Run the machine verifier after initializing machine functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243128 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 17:44:49 +00:00
Mehdi Amini 15e1e7f179 Remove access to the DataLayout in the TargetMachine
Summary:
Replace getDataLayout() with a createDataLayout() method to make
explicit that it is intended to create a DataLayout only and not
accessing it for other purpose.

This change is the last of a series of commits dedicated to have a
single DataLayout during compilation by using always the one owned
by the module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11103

(cherry picked from commit 5609fc56bca971e5a7efeaa6ca4676638eaec5ea)

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243114 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 16:04:22 +00:00
Mehdi Amini 26be214232 Revert "Remove access to the DataLayout in the TargetMachine"
This reverts commit 0f720d984f.

It breaks clang too badly, I need to prepare a proper patch for clang
first.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243089 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 03:36:55 +00:00
Mehdi Amini 0f720d984f Remove access to the DataLayout in the TargetMachine
Summary:
Replace getDataLayout() with a createDataLayout() method to make
explicit that it is intended to create a DataLayout only and not
accessing it for other purpose.

This change is the last of a series of commits dedicated to have a
single DataLayout during compilation by using always the one owned
by the module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11103

(cherry picked from commit 5609fc56bca971e5a7efeaa6ca4676638eaec5ea)

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243083 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 01:44:39 +00:00
NAKAMURA Takumi 152d200641 MIRParser/LLVMBuild.txt: Add MC for MCRegisterInfo::getDwarfRegNum().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243081 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 01:12:36 +00:00
NAKAMURA Takumi af9a5bc3e4 Reorder alphabetically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243080 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 01:12:28 +00:00
Alex Lorenz 832202c797 MIR Serialization: Serialize the '.cfi_offset' CFI instruction.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243062 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-23 23:09:07 +00:00
Sanjay Patel c3bac701a5 fix crash in machine trace metrics due to processing dbg_value instructions (PR24199)
The test in PR24199 ( https://llvm.org/bugs/show_bug.cgi?id=24199 ) crashes because machine
trace metrics was not ignoring dbg_value instructions when calculating data dependencies.

The machine-combiner pass asks machine trace metrics to calculate an instruction trace, 
does some reassociations, and calls MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval()
along with MachineTraceMetrics::invalidate(). The dbg_value instructions have their operands
invalidated, but the instructions are not expected to be deleted.

On a subsequent loop iteration of the machine-combiner pass, machine trace metrics would be
called again and die while accessing the invalid debug instructions.

Differential Revision: http://reviews.llvm.org/D11423



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243057 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-23 22:56:53 +00:00
Bruno Cardoso Lopes e7aafe5ecc [PeepholeOptimizer] Refactor optimizeUncoalescable logic
Reapply r242294.

- Create a new CopyRewriter for Uncoalescable copy-like instructions
- Change the ValueTracker to return a ValueTrackerResult

This makes optimizeUncoalescable looks more like optimizeCoalescable and
use the CopyRewritter infrastructure.

This is also the preparation for looking up into PHI nodes in the
ValueTracker.

rdar://problem/20404526

Differential Revision: http://reviews.llvm.org/D11195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242940 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-22 21:30:16 +00:00
Alex Lorenz 6f3ab8dd7b MIR Serialization: Serialize the machine instruction's debug location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242938 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-22 21:15:11 +00:00
Alex Lorenz d02a9a798c MIR Parser: Extract the MDNode parsing code into a separate method. NFC.
This change would allow the machine instruction parser to reuse this method when
parsing the metadata node for the machine instruction's debug location property.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242934 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-22 21:07:04 +00:00
Alex Lorenz 03c5b6047e MIR Serialization: Serialize the metadata machine operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242916 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-22 17:58:46 +00:00
Chandler Carruth f020cb2f75 [PM/AA] Remove all of the dead AliasAnalysis pointers being threaded
through APIs that are no longer necessary now that the update API has
been removed.

This will make changes to the AA interfaces significantly less
disruptive (I hope). Either way, it seems like a really nice cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242882 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-22 09:52:54 +00:00
Jingyue Wu 9764983070 [BranchFolding] do not iterate the aliases of virtual registers
Summary:
MCRegAliasIterator only works for physical registers. So, do not run it
on virtual registers.

With this issue fixed, we can resurrect the BranchFolding pass in NVPTX
backend.

Reviewers: jholewinski, bkramer

Subscribers: henryhu, meheff, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11174

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242871 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-22 04:16:52 +00:00
Alex Lorenz 1b75dd2bc2 MIR Serialization: Start serializing the CFI operands with .cfi_def_cfa_offset.
This commit begins serialization of the CFI index machine operands by
serializing one kind of CFI instruction - the .cfi_def_cfa_offset instruction.

Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242845 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-21 22:28:27 +00:00
Bruno Cardoso Lopes a14dff356b [AsmPrinter] Check for valid constants in handleIndirectSymViaGOTPCRel
Check whether BaseCst is valid before extracting a GlobalValue.
This fixes PR24163.

Patch by David Majnemer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242840 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-21 21:45:42 +00:00
Alex Lorenz 5938be0e84 MIR Parser: Reuse the function 'lexName' when lexing global value tokens. NFC.
This commit refactors the function 'maybeLexGlobalValue' so that now it reuses
the function 'lexName' when lexing a named global value token.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242837 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-21 21:23:08 +00:00
Alex Lorenz 65671bf628 MIR Serialization: Serialize the external symbol machine operands.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242806 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-21 16:59:53 +00:00
JF Bastien 9994b911f4 Targets: commonize some stack realignment code
This patch does the following:
* Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`.
* Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute.

Multiple targets duplicated the same `needsStackRealignment` code:
 - Aarch64.
 - ARM.
 - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has.
 - PowerPC.
 - WebAssembly.
 - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has.

The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects:
 - AMDGPU
 - BPF
 - CppBackend
 - MSP430
 - NVPTX
 - Sparc
 - SystemZ
 - XCore
 - Out-of-tree targets
This is a breaking change! `make check` passes.

The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation.

`needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone.

Reviewers: sunfish

Subscribers: aemerson, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11160

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242727 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20 22:51:32 +00:00
Matthias Braun 679d26ce56 MachineScheduler: Restrict macroop fusion to data-dependent instructions.
Before creating a schedule edge to encourage MacroOpFusion check that:
- The predecessor actually writes a register that the branch reads.
- The predecessor has no successors in the ScheduleDAG so we can
  schedule it in front of the branch.

This avoids skewing the scheduling heuristic in cases where macroop
fusion cannot happen.

Differential Revision: http://reviews.llvm.org/D10745

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242723 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20 22:34:44 +00:00
Alex Lorenz 0e4484f44d MIR Serialization: Initial serialization of machine constant pools.
This commit implements the initial serialization of machine constant pools and
the constant pool index machine operands. The constant pool is serialized using
a YAML sequence of YAML mappings that represent the constant values.
The target-specific constant pool items aren't serialized by this commit.

Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242707 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20 20:51:18 +00:00
Sanjoy Das a4b0d863f9 [ImplicitNullChecks] Work with implicit defs.
Summary:
This change generalizes the implicit null checks pass to work with
instructions that don't have any explicit register defs.  This lets us
use X86's `cmp` against memory as faulting load instructions.

Reviewers: reames, JosephTremoulet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11286

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242703 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20 20:31:39 +00:00
Alex Lorenz 40fefe0084 MIR Parser: Add support for quoted named global value operands.
This commit extends the machine instruction lexer and implements support for
the quoted global value tokens. With this change the syntax for the global value
identifier tokens becomes identical to the syntax for the global identifier
tokens from the LLVM's assembly language.

Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242702 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20 20:31:01 +00:00
Simon Pilgrim e13745001d [DAGCombiner] Fixed minor typo that was missed in D9097.
We don't bitcast the UNDEFs - that is done in visitVECTOR_SHUFFLE, and the getValueType should come from the operand's SDValue not the SDNode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242640 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-19 11:31:40 +00:00
Simon Pilgrim c365e7e2b5 Remove TargetInstrInfo::canFoldMemoryOperand
canFoldMemoryOperand is not actually used anywhere in the codebase - all existing users instead call foldMemoryOperand directly when they wish to fold and can correctly deduce what they need from the return value. 

This patch removes the canFoldMemoryOperand base function and the target implementations; only x86 had a real (bit-rotted) implementation, although AMDGPU had a preparatory stub that had never needed to be completed.

Differential Revision: http://reviews.llvm.org/D11331

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242638 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-19 10:50:53 +00:00
Simon Pilgrim cb29c8d9cf Use SDValue bool check. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242636 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-19 09:56:36 +00:00
Benjamin Kramer 0836620230 [AggressiveAntiDepBreaker] Use range loops for multimap access.
No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242620 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-18 20:05:10 +00:00
Quentin Colombet 3df507cbfa [RAGreedy] Add an experimental deferred spilling feature.
The idea of deferred spilling is to delay the insertion of spill code until the
very end of the allocation. A "candidate" to spill variable might not required
to be spilled because of other evictions that happened after this decision was
taken. The spirit is similar to the optimistic coloring strategy implemented in
Preston and Briggs graph coloring algorithm.

For now, this feature is highly experimental. Although correct, it would require
much more modification to properly model the effect of spilling.

Anyway, this early patch helps prototyping this feature.

Note: The test case cannot unfortunately be reduced and is probably fragile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242585 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-17 23:04:06 +00:00