Commit Graph

13269 Commits

Author SHA1 Message Date
Eric Christopher
b83e2bbfbc Grammar-o in function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-02 02:11:47 +00:00
Eric Christopher
61cafd1449 Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151874 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-02 01:57:55 +00:00
Eric Christopher
50e266135e If the linkage name doesn't exist we're supposed to emit a reference
to the string table for the function name, not the function name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-02 01:57:52 +00:00
Eric Christopher
7550f7dce6 Revert "Reorder the sections being output to reduce the number of assembler"
The inline table needs to be constructed ahead of time so that it doesn't try to
create new strings while we're emitting everything.

This reverts commit a8ff9bccb399183cdd5f1c3cec2bda763664b4b0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-02 00:30:24 +00:00
Eric Christopher
12313a56ec Reorder the sections being output to reduce the number of assembler
fixups that are being used to determine section offsets. Reduces
the total number of fixups by 50% for a non-trivial testcase.

Part of rdar://10413936

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 22:50:31 +00:00
Michael J. Spencer
647c0ce48c Minimal changes for LLVM to compile under VS11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151849 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 22:42:52 +00:00
James Molloy
391016025a Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even though they could have sideeffects.
Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 14:32:18 +00:00
Jakob Stoklund Olesen
66c994c2db Make InlineSpiller bundle-aware.
Simply treat bundles as instructions. Spill code is inserted between
bundles, never inside a bundle.  Rewrite all operands in a bundle at
once.

Don't attempt and memory operand folding inside bundles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 01:43:25 +00:00
Jakob Stoklund Olesen
741981adf3 Move getBundleStart() into MachineInstrBundle.h.
This allows the function to be inlined, and makes it suitable for use in
getInstructionIndex().

Also provide a const version. C++ is great for touch typing practice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 01:26:01 +00:00
Lang Hames
275ff9bb17 Don't redundantly copy implicit operands when rematerializing.
While we're at it - don't copy vreg implicit operands while rematerializing.
This fixes PR12138.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 00:41:17 +00:00
Benjamin Kramer
f1820b54e4 LegalizeIntegerTypes: Reorder operations in the "big shift by small amount" optimization, making the lives of later passes easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 13:27:00 +00:00
Jakob Stoklund Olesen
a36fe73645 Add an analyzeVirtReg() function.
This function does more or less the same as
MI::readsWritesVirtualRegister(), but it supports bundles as well.

It also determines if any constraint requires reading and writing
operands to use the same register.  Most clients want to know.

Use the more modern MO.readsReg() instead of trying to sort out undefs
and partial redefines.  Stop supporting the extra full <imp-def> operand
as an alternative to <def,undef> sub-register defines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151690 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 01:40:37 +00:00
Jakob Stoklund Olesen
30e98a03a3 Move the operand iterator into MachineInstrBundle.h where it belongs.
Extract a base class and provide four specific sub-classes for iterating
over const/non-const bundles/instructions.

This eliminates the mystery bool constructor argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 00:33:41 +00:00
Lang Hames
1485455be0 Kill off LiveRangeEdit::getNewVRegs and LiveRangeEdit::getUselessVRegs. These
methods are no longer needed now that LinearScan has gone away.

(Contains tweaks trivialSpillEverywhere to enable the removal of getNewVRegs).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 22:07:24 +00:00
Evan Cheng
4bfcd4acbc Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 18:51:51 +00:00
Benjamin Kramer
a3b2121ccf Fix off-by one in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 18:37:06 +00:00
Benjamin Kramer
3bf15ced2b LegalizeIntegerTypes: Reenable the large shift with small amount optimization.
To avoid problems with zero shifts when getting the bits that move between words
we use a trick: first shift the by amount-1, then do another shift by one. When
amount is 0 (and size 32) we first shift by 31, then by one, instead of by 32.

Also fix a latent bug that emitted the low and high words in the wrong order
when shifting right.

Fixes PR12113.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151637 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 17:58:00 +00:00
Daniel Dunbar
20bd5296ce Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 15:36:07 +00:00
Nadav Rotem
1c239200e4 Code cleanup following CR by Duncan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151627 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 14:13:19 +00:00
Nadav Rotem
21ef70ed4f Fix a bug in the code that builds SDNodes from vector GEPs.
When the GEP index is a vector of pointers, the code that calculated the size
of the element started from the vector type, and not the contained pointer type.
As a result, instead of looking at the data element pointed by the vector, this
code used the size of the vector. This works for 32bit members (on 32bit
systems), but not for other types. Added code to peel the vector type and
added a test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 11:54:05 +00:00
Evan Cheng
ec52aaa12f Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 06:42:03 +00:00
Jakob Stoklund Olesen
2129a0f677 Handle regmasks in MachineCSE.
Don't attempt to extend physreg live ranges across calls.

<rdar://problem/10942095>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 02:08:50 +00:00
Jakob Stoklund Olesen
9ca12d2e2f Handle regmasks in the machine code verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 01:42:41 +00:00
Chad Rosier
921c9bd91f Fix 80-column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 00:23:01 +00:00
Evan Cheng
b266cd0e98 Fix for PR12090: clear def maps of aliases when visiting a copy. e.g.
%S5<def> = COPY %S0<kill>
First clear def map of Q1, etc.

No small test case available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 21:46:42 +00:00
Jakob Stoklund Olesen
121b179edf Update machine code verifier.
After the SlotIndex slot names were updated, it is possible to apply
stricter checks to live intervals.

Also treat bundles as bags of operands when checking live intervals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151531 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 18:24:30 +00:00
Lang Hames
c69cbd0a74 Make the peephole optimizer clear kill flags on a vreg if it's about to add new
uses of the vreg, since the old kills may no longer be valid.  This was causing
-verify-machineinstrs to complain about uses after kills, and could potentially
have been causing subtle register allocation issues, but I haven't come across a
test case yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-25 02:01:00 +00:00
Lang Hames
3b26eb6294 Fixed typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-25 00:46:38 +00:00
Jakob Stoklund Olesen
f79b489571 Add missing static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 21:52:44 +00:00
Jakob Stoklund Olesen
27bc818eaf Add a -stress-regalloc=<N> option.
This will limit all register classes to N registers in order to stress
test register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151379 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 18:34:20 +00:00
Hal Finkel
f77c03a859 Don't crash when a glue node contains an internal CopyToReg
This is necessary to support the existing ppc lowering code for indirect calls.
Fixes PR12071.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151373 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 17:53:59 +00:00
Benjamin Kramer
8b93ff298c SDAGBuilder: Remove register sets that were never read and prune dead code surrounding it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151364 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 14:01:17 +00:00
Nick Lewycky
aaad5f2b9a ScheduleDAGInstrs.h:155: warning: suggest parentheses around &&' within ||'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151355 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 07:59:05 +00:00
Andrew Trick
702d489a95 PostRA sched: speed up physreg tracking by not abusing SparseSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151348 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 07:04:55 +00:00
Pete Cooper
d18134f116 Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151342 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 03:51:49 +00:00
Eric Christopher
178606d92e If the Address of a variable is an argument then treat the entire
variable declaration as an argument because we want that address
anyhow for our debug information.

This seems to fix rdar://9965111, at least we have more debug
information than before and from reading the assembly it appears
to be the correct location.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151335 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 01:59:08 +00:00
Eric Christopher
5b13ed1ac9 Tabs, formatting and long lines oh my!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 01:59:01 +00:00
Bill Wendling
9e8ceb0bac Allow an integer to be converted into an MMX type when it's used in an inline
asm.
<rdar://problem/10106006>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 23:25:25 +00:00
Benjamin Kramer
b6bd8ccd02 BitVectorize loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 19:29:25 +00:00
Benjamin Kramer
46252d8ea1 post-ra-sched: Turn the KillIndices vector into a bitvector, it only stored two meaningful states.
Rename it to LiveRegs to make it more clear what's stored inside.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151273 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 19:15:40 +00:00
Benjamin Kramer
49b726c339 post-ra-sched: Replace a std::set of regs with a bitvector.
Assuming that a single std::set node adds 3 control words, a bitvector
can store (3*8+4)*8=224 registers in the allocated memory of a single
element in the std::set (x86_64). Also we don't have to call malloc
for every register added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 18:28:32 +00:00
Jakob Stoklund Olesen
976647d95d Make calls scheduling boundaries post-ra.
Before register allocation, instructions can be moved across calls in
order to reduce register pressure.  After register allocation, we don't
gain a lot by moving callee-saved defs across calls.  In fact, since the
scheduler doesn't have a good idea how registers are used in the callee,
it can't really make good scheduling decisions.

This changes the schedule in two ways: 1. Latencies to call uses and
defs are no longer accounted for, causing some random shuffling around
calls.  This isn't really a problem since those uses and defs are
inaccurate proxies for what happens inside the callee.  They don't
represent registers used by the call instruction itself.

2. Instructions are no longer moved across calls.  This didn't happen
very often, and the scheduling decision was made on dubious information
anyway.

As with any scheduling change, benchmark numbers shift around a bit,
but there is no positive or negative trend from this change.

This makes the post-ra scheduler 5% faster for ARM targets.

The secret motivation for this patch is the introduction of register
mask operands representing call clobbers.  The most efficient way of
handling regmasks in ScheduleDAGInstrs is to model them as barriers for
physreg live ranges, but not for virtreg live ranges.  That's fine
pre-ra, but post-ra it would have the same effect as this patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151265 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 17:54:21 +00:00
Benjamin Kramer
92fc97afa7 Strip a layer of boilerplate from the VLIWPacketizer by storing the scheduler as an opaque pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 13:39:13 +00:00
Anton Korobeynikov
1d2d5a0227 Fix to make sure that a comdat group gets generated correctly for a static member
of instantiated C++ templates.

Patch by Kristof Beyls!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 10:36:04 +00:00
Eric Christopher
0822e010d1 More newline cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151235 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 03:39:43 +00:00
Eric Christopher
244136770b Add some handy-dandy newlines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 03:39:39 +00:00
Andrew Trick
63d578b5aa misched: cleanup reaching def computation
Ignore undef uses completely.
Use a more explicit SlotIndex API.
Add more explicit comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 03:16:24 +00:00
Andrew Trick
81a682a4c0 PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.
Added array subscript to SparseSet for convenience.
Slight reorg to make it easier to manage the def/use sets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151228 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:52:38 +00:00
Jakob Stoklund Olesen
f19a5926cb Handle regmasks in FixupKills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:22:15 +00:00
Jakob Stoklund Olesen
bbad2f1040 Handle regmasks in CriticalAntiDepBreaker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151223 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:15:26 +00:00