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Author SHA1 Message Date
Evan Cheng
b13bafe5c1 On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73720 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-18 20:37:15 +00:00
Evan Cheng
f9f1da17f8 - Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints. 
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-18 02:04:01 +00:00
Bob Wilson
ff6de36558 ARM unified syntax is not specific to ELF; use it for Darwin, too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73665 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-18 00:36:17 +00:00
Anton Korobeynikov
7c4f7dd43a Fix asm string from MOVi16 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73661 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-17 23:43:36 +00:00
Anton Korobeynikov
d61eca5330 Thumb2 instructions are enabled only in unified assembler mode. 
Emit switch directive for it. I have no idea whether this is
requirement for Darwin or not.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73660 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-17 23:43:18 +00:00
Anton Korobeynikov
52237119a9 Initial support for some Thumb2 instructions. 
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-17 18:13:58 +00:00
Douglas Gregor
1555a23335 Introduce new headers whose inclusion forces linking and 
initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73543 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 20:12:29 +00:00
Anton Korobeynikov
385f5a99ec Address review comments: add 3 ARM calling conventions. 
Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73530 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 18:50:49 +00:00
Anton Korobeynikov
2932795309 GNU as refuses to assemble "pop {}" instruction. Do not emit such 
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73529 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 18:49:08 +00:00
Evan Cheng
88cc7c4194 On Darwin, frame pointer r7 is never available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73434 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 22:32:01 +00:00
Anton Korobeynikov
bb62962342 Rename methods for the sake of consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73428 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 21:46:20 +00:00
Evan Cheng
675860758e Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 21:18:20 +00:00
Evan Cheng
d780f35794 Do not form ldrd / strd if the two dests / srcs are the same. Code clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73413 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 20:54:56 +00:00
Evan Cheng
7f04428738 Silence a warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73406 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 19:36:32 +00:00
Evan Cheng
358dec5180 Part 1. 
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 08:28:29 +00:00
Evan Cheng
e7d6df7353 Add a ARM specific pre-allocation pass that re-schedule loads / stores from 
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-13 09:12:55 +00:00
Evan Cheng
cd799b99cb Mark some pattern-less instructions as neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-12 20:46:18 +00:00
Anton Korobeynikov
2e7ccfce98 Typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73098 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 22:59:50 +00:00
Anton Korobeynikov
dada95b5b3 Revert hunk commited by accident 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73097 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 22:57:18 +00:00
Anton Korobeynikov
0eebf653a7 The attached patches implement most of the ARM AAPCS-VFP hard float 
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 22:53:56 +00:00
Anton Korobeynikov
fbbf1eeccf Separate V6 from V6T2 since the latter has some extra nice instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73085 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 21:20:36 +00:00
Anton Korobeynikov
a7b0ded2a2 Add helper for checking of Thumb1 mode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73080 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 20:31:02 +00:00
Dan Gohman
2392efef1b Add explicit keywords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72969 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-05 23:05:51 +00:00
Evan Cheng
925492279a Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-05 19:08:58 +00:00
Evan Cheng
87d59e49e9 When merging multiple load / store instructions. Use the DebugLoc of the first one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72952 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-05 18:19:23 +00:00
Evan Cheng
5ba71887f9 Code clean up: return vector by reference rather than by value. No functionality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72950 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-05 17:56:14 +00:00
Dan Gohman
c965ee223c Remove some unnecessary #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72948 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-05 16:32:58 +00:00
Evan Cheng
1488326156 Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 01:15:28 +00:00
Evan Cheng
70fd60bd57 Temporarily revert 72756 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 07:40:47 +00:00
Evan Cheng
9d5fb981b0 Fold preceding / trailing base inc / dec into the single load / store as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 06:14:58 +00:00
Anton Korobeynikov
70459bef9c Implement review feedback. Make thumb2 'normal' subtarget feature 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72698 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-01 20:00:48 +00:00
Bruno Cardoso Lopes
434dd4fd94 Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72697 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-01 19:57:37 +00:00
Anton Korobeynikov
d260c248ab Do not emit "generic" CPU string. This fixes PR4291. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72696 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-01 19:03:17 +00:00
Bruno Cardoso Lopes
a3f99f9033 First patch in the direction of splitting MachineCodeEmitter in two subclasses: 
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-30 20:51:52 +00:00
Bill Wendling
51b16f4737 Untabification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-30 01:09:53 +00:00
Anton Korobeynikov
d4022c3fbb Add placeholder for thumb2 stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-29 23:41:08 +00:00
Chris Lattner
0c85aabfdc fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72395 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-25 19:51:07 +00:00
Anton Korobeynikov
6d7d2aa38a Add ARMv7 architecture, Cortex processors and different FPU modes handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-23 19:51:43 +00:00
Anton Korobeynikov
88ce667003 Emit ARM Build Attributes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72336 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-23 19:51:20 +00:00
Anton Korobeynikov
41a024385f Propagate CPU string out of SubtargetFeatures 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-23 19:50:50 +00:00
Bob Wilson
2f95461ee2 Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls 
for ARM.  This fixes rdar://6908807.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72269 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-22 17:38:41 +00:00
Bob Wilson
261f2a2337 Minor formatting fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72172 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-20 16:30:25 +00:00
Bob Wilson
6aa219a18c Fix pr4227: Handle large immediate values in inline assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72138 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-19 21:27:57 +00:00
Bob Wilson
86c212e894 Follow up on new support for memory operands in ARM inline assembly. 
This fixes pr4233.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72115 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-19 18:33:02 +00:00
Bob Wilson
04746eae49 Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and 
the stack.  Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72106 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-19 10:02:36 +00:00
Bob Wilson
224c244f56 Fix pr4091: Add support for "m" constraint in ARM inline assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72105 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-19 05:53:42 +00:00
Bob Wilson
e6abdffe06 Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has 
to run last because it needs to know the exact size and position of every
basic block.  Currently CodePlacementOpt is set up to run last.  It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72037 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-18 20:55:32 +00:00
Jim Grosbach
f957012866 Update the names of the exception handling sjlj instrinsics to 
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71758 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-14 00:46:35 +00:00
Jim Grosbach
6aa7197fb5 Spelling correction s/builting/builtin/ and remove trailing whitespace in a few places 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71735 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-13 22:32:43 +00:00
Evan Cheng
6ebf7bc740 Run code placement optimization for targets that want it (arm and x86 for now). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-13 21:42:09 +00:00