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32242 Commits

Author SHA1 Message Date
Hao Liu
7d3a44a692 [AArch64]Fix PR21675, a bug about lowering llvm.ctpop.i32. We should noot use "DAG.getUNDEF(MVT::v8i8)" to get all zero vector. 
Patch by Wei-cheng Wang.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227550 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 02:13:53 +00:00
Eric Christopher
dd5e9f624b Use the cached subtarget in PPCFrameLowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227548 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 02:11:26 +00:00
Eric Christopher
87dd120c6a Migrate some of PPC away from the use of bare getSubtarget/getSubtargetImpl. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227547 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 02:11:24 +00:00
Eric Christopher
31f58f2c74 Migrage PPCRegisterInfo to use the cached subtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227546 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 02:11:21 +00:00
Eric Christopher
99a3df3401 Migrate a bare getSubtarget call to query the MachineFunction 
for the target dependent one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227542 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 01:50:09 +00:00
Eric Christopher
b42dc65111 Migrate NVPTXISelLowering to take the subtarget that it's dependent 
upon as an argument and store/use that in the entire function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227541 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 01:50:07 +00:00
Eric Christopher
f66d626182 Remove unused argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227539 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 01:41:01 +00:00
Eric Christopher
7417d92e56 Migrate NVPTXISelDAGToDAG's getSubtarget to a runOnMachineFunction 
version. Update NVPTXInstrInfo accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227538 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 01:40:59 +00:00
Eric Christopher
7c185f3674 Remove calls to bare getSubtarget and clean up the functions 
accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227535 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 01:30:01 +00:00
Eric Christopher
1ed01c9439 Remove a few getSubtarget calls in AArch64 pass manager initialization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227531 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 01:10:26 +00:00
Eric Christopher
3b386bfcd2 Clean up some uses of getSubtarget in AArch64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227530 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 01:10:24 +00:00
Eric Christopher
5e337ee512 This only needs TargetInstrInfo, not the specialized one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227529 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 01:10:18 +00:00
Reid Kleckner
4c757e0907 x86: Remove unused variables not caught by MSVC =P 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227520 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 00:05:39 +00:00
Reid Kleckner
c9fbc97e95 x86: Fix large model calls to __chkstk for dynamic allocas 
In the large code model, we now put __chkstk in %r11 before calling it.

Refactor the code so that we only do this once. Simplify things by using
__chkstk_ms instead of __chkstk on cygming. We already use that symbol
in the prolog emission, and it simplifies our logic.

Second half of PR18582.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227519 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 23:58:04 +00:00
Eric Christopher
5d51c0ee04 Remove unnecessary calls to getSubtarget/getSubtargetImpl from the 
MSP430 backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227517 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 23:46:42 +00:00
Eric Christopher
a5119bd010 Remove unused header. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227516 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 23:46:39 +00:00
Sanjay Patel
65d9a05c76 Change SmallVector param to the more general ArrayRef; NFCI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227514 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 23:35:04 +00:00
Eric Christopher
ca6d2a825c Get rid of a few calls through the subtarget to get the ABI 
that's actually sitting on the target machine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227513 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 23:27:45 +00:00
Eric Christopher
2d64c553b4 Remove most of the TargetMachine::getSubtarget/getSubtargetImpl 
calls that don't take a Function argument from Mips. Notable
exceptions: the AsmPrinter and MipsTargetObjectFile. The
latter needs to be fixed, and the former will be fixed when the
general AsmPrinter changes happen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227512 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 23:27:36 +00:00
Reid Kleckner
850420cd14 x86: Remove the W64ALLOCA pseudo 
This is just an alias for CALL64pcrel32, and we can just use that opcode
with explicit defs in the MI.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227508 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 23:09:37 +00:00
Chad Rosier
880af70fa1 [AArch64] Add INITIALIZE_PASS macros to AArch64A57FPLoadBalancing. 
These are needed so this pass will produce output when
e.g. -print-after-all is used.

Phabricator Review: http://reviews.llvm.org/D7264
Patch by Geoff Berry <gberry@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227506 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 22:57:37 +00:00
Reid Kleckner
cb867e4ac4 Update comments to use unreachable instead of llvm.trap, as implemented now 
win64: Call __chkstk through a register with the large code model

Fixes half of PR18582. True dynamic allocas will still have a
CALL64pcrel32 which will fail.

Reviewers: majnemer

Differential Revision: http://reviews.llvm.org/D7267

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227503 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 22:33:00 +00:00
Colin LeMahieu
5a75088c2f [Hexagon] Organizing tests and adding a few missing jump instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227498 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 21:47:15 +00:00
Colin LeMahieu
d6ce18cdf9 [Hexagon] Adding missing instruction encodings and tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227495 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 21:30:22 +00:00
Colin LeMahieu
d742d5db60 [Hexagon] Adding alu vector instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227493 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 21:09:30 +00:00
David Blaikie
0cb00dbc56 Matching ARM change for r227481: DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227488 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 20:23:47 +00:00
Matt Arsenault
fa711758df R600/SI: Implement enableAggressiveFMAFusion 
Add tests for the various combines. This should
always be at least cycle neutral on all subtargets for f64,
and faster on some. For f32 we should prefer selecting
v_mad_f32 over v_fma_f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227484 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 19:34:32 +00:00
Matt Arsenault
c416d94735 R600/SI: Add subtarget feature for if f32 fma is fast 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227483 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 19:34:25 +00:00
Matt Arsenault
30a5d21457 R600/SI: Fix tonga's basic scheduling model 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227482 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 19:34:18 +00:00
David Blaikie
1ba26f8da1 DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps 
The use of the DbgLoc in FastISel is probably something we should fix.
It's prone to leaking the wrong location into instructions - we should
have a clear chain of custody from the debug location of an IR
Instruction to that of a MachineInstr to avoid such leakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227481 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 19:09:18 +00:00
Rafael Espindola
9936b80df5 Compute the ELF SectionKind from the flags. 
Any code creating an MCSectionELF knows ELF and already provides the flags.

SectionKind is an abstraction used by common code that uses a plain
MCSection.

Use the flags to compute the SectionKind. This removes a lot of
guessing and boilerplate from the MCSectionELF construction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227476 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 17:33:21 +00:00
Colin LeMahieu
dec5091220 [Hexagon] Deleting old variants of intrinsics and adding missing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227474 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 17:26:56 +00:00
Colin LeMahieu
f1b4917f1b [Hexagon] Adding CR intrinsic tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227463 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 16:55:37 +00:00
Tom Stellard
882d1b71e0 R600/SI: Remove stray debug statements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227462 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 16:55:28 +00:00
Tom Stellard
51a3c27d6e R600/SI: Define a schedule model and enable the generic machine scheduler 
The schedule model is not complete yet, and could be improved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227461 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 16:55:25 +00:00
Colin LeMahieu
48a3c8261f [Hexagon] Deleting unused classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227460 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 16:35:38 +00:00
Robert Lougher
1031549bec [X86] Use single add/sub for large stack offsets 
For large stack offsets the compiler generates multiple immediate mode
sub/add instructions in the prologue/epilogue.  This patch makes the
compiler place the final amount to be added/subtracted into a register,
which is then added/substracted with a single operation.

Differential Revision: http://reviews.llvm.org/D7226


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227458 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 16:18:29 +00:00
Colin LeMahieu
c7260e2ffa [Hexagon] Adding XTYPE/PRED intrinsic tests. Converting predicate types to i32 instead of i1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227457 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 16:08:43 +00:00
Bill Schmidt
a5ea0b50a4 [PowerPC] Complete setting the baseline for ppc64le 
Patch by Nemanja Ivanovic.

As was uncovered by the failing test case (when run on non-PPC
platforms), the feature set when compiling with -march=ppc64le was not
being picked up. This change ensures that if the -mcpu option is not
specified, the correct feature set is picked up regardless of whether
we are on PPC or not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227455 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 15:59:09 +00:00
Rafael Espindola
248a6cf2c0 Remove MergeableConst. 
Only the specific ones (MergeableConst4, MergeableConst8, MergeableConst16) are
handled specially.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227440 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 14:12:41 +00:00
Vladimir Medic
d0fb85865a [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227430 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 11:33:41 +00:00
Eric Christopher
bd2a700208 Remove getSubtargetImpl from AArch64ISelLowering and cache the 
correct subtarget by passing it in during the constructor as
TargetLowering is Subtarget specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227402 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 00:19:42 +00:00
Eric Christopher
3dd7e82123 Remove getSubtargetImpl from ARMISelLowering and cache the 
correct subtarget by passing it in during the constructor as
TargetLowering is Subtarget specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227401 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 00:19:39 +00:00
Eric Christopher
92185fdb9f Small cleanup in ARMFastISel initialization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227400 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 00:19:37 +00:00
Eric Christopher
a6deca3e1b Migrate ARM except for TTI, AsmPrinter, and frame lowering 
away from getSubtargetImpl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227399 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 00:19:33 +00:00
Sanjay Patel
d5502c5f13 fix typos; NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227386 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 22:37:32 +00:00
Colin LeMahieu
24373e35a4 [Hexagon] Updating several V5 intrinsics and adding FP tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227379 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 22:08:16 +00:00
Simon Pilgrim
d0e8688ebc Spelling fixes. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227376 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 22:03:52 +00:00
Simon Pilgrim
5d8772fef5 Line endings fix. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227374 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 21:56:52 +00:00
Zoran Jovanovic
7624914c14 [mips][microMIPS] Implement SWM and LWM aliases 
Differential Revision: http://reviews.llvm.org/D5820


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227373 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 21:52:27 +00:00