they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6564 91177308-0d34-0410-b5e6-96231b3b80d8
* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6560 91177308-0d34-0410-b5e6-96231b3b80d8
None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6549 91177308-0d34-0410-b5e6-96231b3b80d8
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.
Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.
The other changes are just elimination of unnecessary spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6437 91177308-0d34-0410-b5e6-96231b3b80d8
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
their fields were totally screwed up. This seems to fix the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6429 91177308-0d34-0410-b5e6-96231b3b80d8
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6388 91177308-0d34-0410-b5e6-96231b3b80d8
