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88 Commits

Author SHA1 Message Date
David Goodwin
3ca524e336 Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75254 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 17:03:29 +00:00
Evan Cheng
cd799b99cb Mark some pattern-less instructions as neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-12 20:46:18 +00:00
Evan Cheng
38b6fd67a6 Fix a 80 col. violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60901 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-11 22:02:02 +00:00
Dan Gohman
15511cf166 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-03 18:15:48 +00:00
Evan Cheng
7e2cc91d2d Fix fuitos encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59344 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-15 00:40:57 +00:00
Evan Cheng
3c902e81fa fsub{d|s} encoding bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59234 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-13 07:59:48 +00:00
Evan Cheng
3c4a4ffa3d Consolidate formats; fix FCMPED etc. encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59107 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-12 07:18:38 +00:00
Evan Cheng
80a119842d Fix VFP conversion instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59104 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-12 06:41:41 +00:00
Evan Cheng
d06d48d2b5 Fix encoding of single-precision VFP registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59102 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-12 02:19:38 +00:00
Evan Cheng
0a0ab1387a Fix FMDRR encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59088 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-11 22:46:12 +00:00
Evan Cheng
cd8e66a1ef Encode VFP load / store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59084 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-11 21:48:44 +00:00
Evan Cheng
78be83d7c2 Encode VFP conversion instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59074 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-11 19:40:26 +00:00
Evan Cheng
96581d3633 Encode VFP arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59016 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-11 02:11:05 +00:00
Evan Cheng
d87293ce78 Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 08:47:38 +00:00
Jim Grosbach
e5d20f947a udpate header comment: s/VP/VFP/ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56126 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-11 21:41:29 +00:00
Evan Cheng
da47e6e0d0 Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-15 00:03:38 +00:00
Chris Lattner
48be23cd65 rename SDTRet -> SDTNone. 
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-15 22:02:54 +00:00
Chris Lattner
9b37aaf04c get def use info more correct. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-10 05:12:37 +00:00
Evan Cheng
325474e065 Only mark instructions that load a single value without extension as isSimpleLoad = 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45727 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-07 23:56:57 +00:00
Chris Lattner
834f1ce031 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 23:38:27 +00:00
Chris Lattner
2e48a70b35 rename isStore -> mayStore to more accurately reflect what it captures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 08:36:04 +00:00
Chris Lattner
13c6310866 remove explicit isStore flags that are now inferrable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45653 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 05:55:01 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Evan Cheng
6e141fd048 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-12 23:12:09 +00:00
Evan Cheng
071a279e94 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 19:55:27 +00:00
Evan Cheng
0ff94f7fcc Initial JIT support for ARM by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 01:37:15 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Evan Cheng
13ab020ea0 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:08:01 +00:00
Evan Cheng
9ad6f03166 No need for ccop anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:34:09 +00:00
Evan Cheng
c85e832eb7 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:13:32 +00:00
Evan Cheng
2c614c5c69 Mark these instructions clobbersPred. They modify the condition code register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-06 10:17:05 +00:00
Evan Cheng
c6f2f6fbb9 For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37351 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 23:34:19 +00:00
Evan Cheng
44bec52b1b Add PredicateOperand to all ARM instructions that have the condition field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-15 01:29:07 +00:00
Evan Cheng
42d712b306 Switch BCC, MOVCCr, etc. to PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-08 21:08:43 +00:00
Evan Cheng
c4e600362e This is no longer needed after enabling the DAG combiner xform. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36909 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-07 21:29:41 +00:00
Dale Johannesen
4ac075c859 Evan's patch to avoid FPreg->intreg copy for cvt; store to mem 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36693 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 20:54:42 +00:00
Chris Lattner
72939126d4 match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36660 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 00:32:00 +00:00
Evan Cheng
a8e2989ece ARM backend contribution from Apple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-19 07:51:42 +00:00