Commit Graph

29 Commits

Author SHA1 Message Date
David Goodwin
dc4bdcdef1 Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19 16:08:58 +00:00
David Goodwin
710461688b Add callback to allow target to adjust latency of schedule dependency edge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78910 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13 16:05:04 +00:00
David Goodwin
d94a4e5d8d Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78563 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 15:55:25 +00:00
Dan Gohman
748f98f908 Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78362 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 01:26:06 +00:00
Dan Gohman
8906f95006 Eliminate yet another copy of getOpcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76236 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17 20:58:59 +00:00
Dan Gohman
16a2c927e9 Move isLCSSAForm, isLoopInvariant, getCanonicalInductionVariable,
and related functions out of LoopBase and into Loop, since they
are specific to BasicBlock-based loops. This also allows the code
to be moved out-of-line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75523 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-13 22:02:44 +00:00
Dan Gohman
47ac0f0c7c When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.

Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-11 04:27:20 +00:00
Dan Gohman
9e64bbb322 Factor out more code for computing register live-range informationfor
scheduling, and generalize is so that preserves state across
scheduling regions. This fixes incorrect live-range information around
terminators and labels, which are effective region boundaries.

In place of looking for terminators to anchor inter-block dependencies,
introduce special entry and exit scheduling units for this purpose.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64254 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-10 23:27:53 +00:00
Dan Gohman
6dc75fe527 Move ScheduleDAGInstrs.h to be a private header. Front-ends
that used this header to select a scheduling policy should
use SchedulerRegistry.h instead (llvm-gcc and clang were
updated a while ago).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63934 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:12:10 +00:00
Dan Gohman
3311a1f8f0 Fix a post-RA scheduling dependency bug.
If a MachineInstr doesn't have a memoperand but has an opcode that
is known to load or store, assume its memory reference may alias
*anything*, including stack slots which the compiler completely
controls.

To partially compensate for this, teach the ScheduleDAG building
code to do basic getUnderlyingValue analysis. This greatly
reduces the number of instructions that require restrictive
dependencies. This code will need to be revisited when we start
doing real alias analysis, but it should suffice for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63370 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-30 02:49:14 +00:00
Dan Gohman
f7119393a9 Instead of adding dependence edges between terminator instructions
and every other instruction in their blocks to keep the terminator
instructions at the end, teach the post-RA scheduler how to operate
on ranges of instructions, and exclude terminators from the range
of instructions that get scheduled.

Also, exclude mid-block labels, such as EH_LABEL instructions, and
schedule code before them separately from code after them. This
fixes problems with the post-RA scheduler moving code past
EH_LABELs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62366 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-16 22:10:20 +00:00
Dan Gohman
79ce276083 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15 19:20:50 +00:00
Dan Gohman
0b1d4a798d Clean up the atomic opcodes in SelectionDAG.
This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.

This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61389 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23 21:37:04 +00:00
Dan Gohman
c9a5b9e38b Rename BuildSchedUnits to BuildSchedGraph, and refactor the
code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61376 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23 18:36:58 +00:00
Dan Gohman
237dee1259 Use isTerminator() instead of isBranch()||isReturn() in
several places. isTerminator() returns true for a superset
of cases, and includes things like FP_REG_KILL, which are
nither return or branch but aren't safe to move/remat/etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61373 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23 17:28:50 +00:00
Dan Gohman
8749b61178 Add initial support for back-scheduling address computations,
especially in the case of addresses computed from loop induction
variables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16 03:35:01 +00:00
Dan Gohman
3f23744df4 Fix some register-alias-related bugs in the post-RA scheduler liveness
computation code. Also, avoid adding output-depenency edges when both
defs are dead, which frequently happens with EFLAGS defs.

Compute Depth and Height lazily, and always in terms of edge latency
values. For the schedulers that don't care about latency, edge latencies
are set to 1.

Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array.
These are all subsumed by the Depth and Height fields.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61073 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16 03:25:46 +00:00
Dan Gohman
4ea8e85e19 Add a simple target-independent heuristic to allow targets with no
instruction itinerary data to back-schedule loads.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61070 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16 02:38:22 +00:00
Dan Gohman
54e4c36a73 Rewrite the SDep class, and simplify some of the related code.
The Cost field is removed. It was only being used in a very limited way,
to indicate when the scheduler should attempt to protect a live register,
and it isn't really needed to do that. If we ever want the scheduler to
start inserting copies in non-prohibitive situations, we'll have to
rethink some things anyway.

A Latency field is added. Instead of giving each node a single
fixed latency, each edge can have its own latency. This will eventually
be used to model various micro-architecture properties more accurately.

The PointerIntPair class and an internal union are now used, which
reduce the overall size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60806 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-09 22:54:47 +00:00
Dan Gohman
a629b48a66 Fix the top-level comments, and fix some 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60707 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-08 17:50:35 +00:00
Dan Gohman
6a9041e5ca Add minimal support for disambiguating memory references. Currently
the main thing this covers is spills to distinct spill slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60517 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-04 01:35:46 +00:00
Dan Gohman
974b5f53f7 Pass the isAntiDep argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59968 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-24 17:24:27 +00:00
Dan Gohman
37d8b3193d Correctly set the isCtrl flag for chain dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59837 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21 19:17:25 +00:00
Dan Gohman
fc626b62b8 Update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59836 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21 19:16:58 +00:00
Dan Gohman
f6b7a47d5d Set the isAntiDep flag in the MachineInstr scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59787 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21 02:38:21 +00:00
Dan Gohman
787782f4ca Use ComputeLatency in the MachineInstr scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59777 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21 01:44:51 +00:00
Dan Gohman
c8c2827993 Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor
some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59761 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21 00:12:10 +00:00
Dan Gohman
8eaf41de8a Treat mid-block labels the same as terminators when building the
MachineInstr scheduling DAG, meaning they implicitly depend on all
preceding defs. This fixes Benchmarks/Shootout-C++/except and
Regression/C++/EH/simple_rethrow in
  -relocation-model=pic -disable-post-RA-scheduler=false
mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59747 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-20 19:58:35 +00:00
Dan Gohman
343f0c0467 Experimental post-pass scheduling support. Post-pass scheduling
is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.

This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.

The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59676 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-19 23:18:57 +00:00