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140 Commits

Author SHA1 Message Date
Chris Lattner
ddf89566a9 This commit changes: 
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-17 19:59:44 +00:00
Chris Lattner
48be23cd65 rename SDTRet -> SDTNone. 
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-15 22:02:54 +00:00
Chris Lattner
9b37aaf04c get def use info more correct. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-10 05:12:37 +00:00
Evan Cheng
325474e065 Only mark instructions that load a single value without extension as isSimpleLoad = 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45727 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-07 23:56:57 +00:00
Chris Lattner
834f1ce031 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 23:38:27 +00:00
Chris Lattner
2e48a70b35 rename isStore -> mayStore to more accurately reflect what it captures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 08:36:04 +00:00
Chris Lattner
13c6310866 remove explicit isStore flags that are now inferrable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45653 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 05:55:01 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Evan Cheng
6e141fd048 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-12 23:12:09 +00:00
Bill Wendling
c69107ca11 Unifacalize the CALLSEQ{START,END} stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44045 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-13 09:19:02 +00:00
Bill Wendling
0f8d9c04d9 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack 
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-13 00:44:25 +00:00
Owen Anderson
20ab29068d Add a flag for indirect branch instructions. 
Target maintainers: please check that the instructions for your target are correctly marked.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-12 07:39:39 +00:00
Evan Cheng
071a279e94 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 19:55:27 +00:00
Evan Cheng
be36798bfe 80 col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41812 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-10 22:22:23 +00:00
Raul Herbster
37fb5b154c ARM instruction table was modified by adding information to generate multiply instruction of V5TE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41626 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:25:47 +00:00
Evan Cheng
0ff94f7fcc Initial JIT support for ARM by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 01:37:15 +00:00
Evan Cheng
7fc77611ef Indexed loads each has 2 outputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40658 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 00:12:08 +00:00
Evan Cheng
ffbaccae02 No more noResults. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-21 00:34:19 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Evan Cheng
13ab020ea0 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:08:01 +00:00
Evan Cheng
9ad6f03166 No need for ccop anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:34:09 +00:00
Evan Cheng
06aae67b83 Do away with ImmutablePredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37961 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:22:46 +00:00
Evan Cheng
04c813d00c PredicateDefOperand -> OptionalDefOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37931 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 01:00:49 +00:00
Evan Cheng
d54874a06d Unbreak the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37914 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 17:13:19 +00:00
Evan Cheng
c85e832eb7 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:13:32 +00:00
Dan Gohman
d45eddd214 Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-26 00:48:07 +00:00
Owen Anderson
0819a9d386 Fix the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37705 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-22 16:59:54 +00:00
Evan Cheng
277f0741c5 Allow predicated immediate ARM to ARM calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37659 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 21:05:09 +00:00
Dan Gohman
82a87a0172 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:48:05 +00:00
Evan Cheng
eaa91b0a1f Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:26:51 +00:00
Evan Cheng
2c614c5c69 Mark these instructions clobbersPred. They modify the condition code register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-06 10:17:05 +00:00
Evan Cheng
c354334ac4 Opcode modifier s comes after condition code. e.g. addlts, not addslt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37388 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 20:51:29 +00:00
Evan Cheng
df4da14948 Make jumptable non-predicable for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37381 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 00:56:15 +00:00
Evan Cheng
fd488edb1d For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37349 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 23:32:06 +00:00
Dale Johannesen
f23b8cf239 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37271 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 22:42:04 +00:00
Dale Johannesen
86d4069666 Add some patterns for PIC PC-relative loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37269 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 22:14:33 +00:00
Evan Cheng
dcc50a4aee Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37199 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 01:53:54 +00:00
Evan Cheng
5ada199246 Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37118 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:50:01 +00:00
Evan Cheng
aeafca0a25 Conditional branch is not a barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37103 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 07:45:54 +00:00
Evan Cheng
44bec52b1b Add PredicateOperand to all ARM instructions that have the condition field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-15 01:29:07 +00:00
Evan Cheng
42d712b306 Switch BCC, MOVCCr, etc. to PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-08 21:08:43 +00:00
Dale Johannesen
caa8055cf5 change per review 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36519 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-28 00:36:37 +00:00
Dale Johannesen
25c1f9e125 Prevent Thumb code from generating ARM instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36518 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 22:17:18 +00:00
Lauro Ramos Venancio
64f4fa5e0e ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36506 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 13:54:47 +00:00
Chris Lattner
120fba91a3 dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36222 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 22:39:58 +00:00
Lauro Ramos Venancio
9996663fc6 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35573 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 01:30:03 +00:00
Lauro Ramos Venancio
b8a93a45f8 bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35381 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-27 16:19:21 +00:00
Lauro Ramos Venancio
64c88d741e bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35218 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 17:57:23 +00:00
Evan Cheng
c70d1849b7 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35207 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 08:11:30 +00:00
Evan Cheng
9f6636ff0c Fix naming inconsistencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:48:02 +00:00