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32724 Commits

Author SHA1 Message Date
Richard Osborne
bfa19bf4c2 Add missing names for the XCore specific LADD and LSUB nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83556 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 17:14:57 +00:00
Dan Gohman
8a261e44f7 Add a form of addPreserved which takes a string argument, to allow passes 
to declare that they preserve other passes without needing to pull in
additional header file or library dependencies. Convert MachineFunctionPass
and CodeGenLICM to make use of this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83555 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 17:00:02 +00:00
Richard Osborne
c96c8e0e81 Add some peepholes for signed comparisons using ashr X, X, 32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83549 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 15:38:17 +00:00
Chris Lattner
8ef27511e3 remove LoopVR pass. According to Nick: 
"LoopVR's logic was copied into ScalarEvolution::getUnsignedRange and 
::getSignedRange. Please delete LoopVR."



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83531 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 06:42:44 +00:00
Bob Wilson
deb3141cf5 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 05:18:18 +00:00
Jim Grosbach
1f30dcbd8d Cleanup up unused R3LiveIn tracking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83522 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 01:50:26 +00:00
Jim Grosbach
65c58daa8b Re-enable register scavenging in Thumb1 by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 01:46:59 +00:00
Jim Grosbach
e40bf5f9f4 bugfix. The target may use virtual registers that aren't tracked for re-use but are allocated by the scavenger. The re-use algorithm needs to watch for that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 01:09:45 +00:00
Bob Wilson
5adf60c03b Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:28:28 +00:00
Bob Wilson
24e04c535f Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:21:01 +00:00
Jeffrey Yasskin
4306963170 In instcombine's debug output, avoid printing ADD for instructions that are 
already on the worklist, and print Visited when an instruction is about to be
visited.  Net, on one input, this reduced the output size by at least 9x.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83510 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:12:24 +00:00
Bob Wilson
0ea38bb939 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 23:54:04 +00:00
Bob Wilson
c67160c010 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 23:39:57 +00:00
Bob Wilson
a4288080e6 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:57:01 +00:00
Jim Grosbach
9f3a559dff reverting thumb1 scavenging default due to test failure while I figure out what's up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:49:41 +00:00
Chris Lattner
831a2bba04 second half of lazy liveness removal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83500 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:49:30 +00:00
Dale Johannesen
5f3663e51d Fix handling of x86 'R' constraint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83499 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:47:20 +00:00
Jim Grosbach
bafa3d9f6a Enable thumb1 register scavenging by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83496 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:26:31 +00:00
Jim Grosbach
ec1434dd89 Enable thumb1 register scavenging by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83494 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:26:14 +00:00
Devang Patel
beab41b874 Extract subprogram and compile unit information from the debug info attached to an instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83491 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:04:08 +00:00
Bob Wilson
b07c171624 Add some instruction encoding bits for NEON load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83490 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 21:53:04 +00:00
Eric Christopher
37c8b86d43 80-column and whitespace fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83489 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 21:14:25 +00:00
Kevin Enderby
5440f6309d Fixed MCSectionMachO::ParseSectionSpecifier to allow an attribute of "none" so 
that a symbol stub section with no attributes can be parsed as in:
.section __TEXT,__picsymbolstub4,symbol_stubs,none,16


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83488 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 20:57:20 +00:00
Bob Wilson
63c9063434 Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 20:49:18 +00:00
Bob Wilson
66a70639da Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 20:30:08 +00:00
Jim Grosbach
b8452b80f4 grammar 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83483 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 19:08:36 +00:00
Bob Wilson
d285575f87 Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:47:39 +00:00
Jim Grosbach
391e1704c2 add initializers for clarity. Add missing assignment of PrevLastUseOp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83481 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:44:24 +00:00
Owen Anderson
c024df648e Remove LazyLiveness from the tree. It doesn't work right now, and I'm not going to have the time 
to finish it any time soon.  If someone's interested it, they can resurrect it from SVN history.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83480 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:40:17 +00:00
Bob Wilson
7708c22baa Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:09:32 +00:00
Kevin Enderby
99e6d4e839 Add another bit of the ARM target assembler to llvm-mc to parse registers 
with writeback, things like "sp!", etc.  Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83477 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:01:35 +00:00
Dan Gohman
2627e08e05 Replace some code for aggressive-remat with MachineInstr::isInvariantLoad, and 
teach it how to recognize invariant physical registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83476 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:47:20 +00:00
Dan Gohman
e33f44cfc5 Replace TargetInstrInfo::isInvariantLoad and its target-specific 
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83475 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:38:06 +00:00
Dan Gohman
2dbc4c84f6 Add a few simple MachineVerifier checks for MachineMemOperands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83474 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:36:00 +00:00
Bob Wilson
ff8952e8a9 Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:24:55 +00:00
Bob Wilson
228c08b8dd Rearrange code for selecting vld2 intrinsics. No functionality change. 
This is just to be more consistent with the forthcoming code for vld3/4.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83470 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:23:09 +00:00
Jim Grosbach
b58f498f75 Add register-reuse to frame-index register scavenging. When a target uses 
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:12:56 +00:00
Devang Patel
7f93f4d66c Do not assume that the module is set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83462 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 16:37:55 +00:00
Torok Edwin
4de86fe0d7 Add PR to this FIXME, looks like I didn't commit this change after all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83457 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 09:22:55 +00:00
Duncan Sands
83ed76869e Make getPointerTo return a const PointerType* rather than 
an unqualified PointerType* because it seems more correct.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83454 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 07:35:19 +00:00
Eric Christopher
00d67db384 Add FreeInst to the "is a call" check for Insts that are calls, but 
not intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83441 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 00:54:08 +00:00
Dan Gohman
bd31b173d2 Fix this comment. The loop header is the loop entry point. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83437 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 00:33:10 +00:00
Anton Korobeynikov
249fb339ad Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) 
and register spills.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83435 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 00:06:35 +00:00
Eric Christopher
0704300d88 While we still have a MallocInst treat it as a call like any other 
for inlining.

When MallocInst goes away this code will be subsumed as part of
calls and work just fine...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83434 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 00:02:18 +00:00
Kevin Enderby
a7ba3a81c0 Added bits of the ARM target assembler to llvm-mc to parse some load instruction 
operands.  Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts.  This is a work in progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83424 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 22:26:42 +00:00
Bob Wilson
3bf12ab860 Add codegen support for NEON vld2 operations on quad registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 22:01:59 +00:00
Bob Wilson
349d82d400 Use copyRegToReg hook to copy registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83421 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 22:01:15 +00:00
Jeffrey Yasskin
0b22873adc r83391 was completely broken since Twines keep references to their inputs, and 
some of the inputs were temporaries.  Here's a real fix for the miscompilation.
Thanks to sabre for pointing out the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83417 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 21:45:26 +00:00
Bob Wilson
a3e8bf8412 Fix a comment typo. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 20:18:46 +00:00
Nicolas Geoffray
35b305863a Bugfix for the CommaSeparated option. The original code was adding the whole 
string at the end of the list, instead of the last comma-separated string.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83405 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 19:55:53 +00:00