Commit Graph

103539 Commits

Author SHA1 Message Date
James Molloy
bfaccd494f Attempt to pacify the bots - this commit requires asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208424 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 16:20:53 +00:00
Rafael Espindola
b4c14b4ad3 Use auto and clang-format this snippet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208421 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 16:01:06 +00:00
Rafael Espindola
f35cc81810 Run clang-format in small sections of code to make a patch easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208419 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 15:49:02 +00:00
Rafael Espindola
2439e5d2c2 Delete trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208416 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 14:39:25 +00:00
Rafael Espindola
f992930d5e Delete trailing white space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208415 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 14:31:07 +00:00
Daniel Sanders
7ef85447c9 [mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-IV that was available in MIPS32

A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.

Depends on D3676

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208414 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 14:06:17 +00:00
Oliver Stannard
e2948385b9 ARM: HFAs must be passed in consecutive registers
When using the ARM AAPCS, HFAs (Homogeneous Floating-point Aggregates) must
be passed in a block of consecutive floating-point registers, or on the stack.
This means that unused floating-point registers cannot be back-filled with
part of an HFA, however this can currently happen. This patch, along with the
corresponding clang patch (http://reviews.llvm.org/D3083) prevents this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208413 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 14:01:47 +00:00
Simon Atanasyan
ba148a1b8f [yaml2obj] Follow-up to the r208228 and r208406. Remove duplicated YAML
map keys.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208412 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 13:57:33 +00:00
Rafael Espindola
dd8ddbf6d3 Remove trailing white space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208411 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 13:54:40 +00:00
Daniel Sanders
08910b08d9 [mips] Remove unused CondMov feature bit
Summary:
No functional change

Depends on D3675

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3676

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208410 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 13:15:07 +00:00
Daniel Sanders
70f6f7ee3e [mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-III that was available in MIPS32

A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.

There's some obvious InstAlias's that ought to be marked MIPS-III but arent.
This is because they are not currently tested. I intend to catch these with
a final pass through the tablegen records to find tablegen records without
ISA annotations.

Depends on D3674

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208408 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 13:02:27 +00:00
NAKAMURA Takumi
a1e2e91de4 Mark yaml2obj-elf-x86-rel.yaml as XFAIL:vg_leak for now. This has two pairs of duplicate hashes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208406 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 11:24:18 +00:00
Andrea Di Biagio
530f9565ef Fix 80 col violation.
No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208405 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 11:08:23 +00:00
Benjamin Kramer
d8d1a7c950 [asan] Stop leaking X86Operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208400 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 09:48:03 +00:00
Daniel Sanders
32650944eb [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6
Summary:
Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these
processors.

I've also included comments to describe removed and re-encoded instructions,
along with placeholder def's for the new instructions but there are no
functional changes to codegen at this point.

Reviewers: jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208399 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 09:46:21 +00:00
Daniel Sanders
6b68224e9a [mips] Added missing daddu test to the valid instruction tests.
Summary: Depends on D3673

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3674

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208398 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 09:32:01 +00:00
Daniel Sanders
76056a0145 [mips] Added missing dsra -> dsrav and sra -> srav aliases.
Summary: dsll, dsrl, sll, and srl already exist.

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3673

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208397 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 09:24:49 +00:00
Alp Toker
8d24d43c95 MemoryBuffer: don't force mmap when stat fails
Fix error handling introduced in r127426 that could result in MemoryBuffers not
having null termination.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208396 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 08:57:32 +00:00
Alp Toker
87ccb2bffd MemoryBuffer: remove unusued definitions
These were made redundant back in r186560.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208395 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 08:57:06 +00:00
NAKAMURA Takumi
ad4480cf8b test/TableGen: Remove XFAIL:vg_leak out of 3 tests corresponding to r208293.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208393 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 08:18:33 +00:00
Rafael Espindola
6454f24187 Don't indent inside a namespace. Don't duplicate a function name in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208389 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 02:56:16 +00:00
David Blaikie
3fb66ae739 Remove use of = default/= delete as they're unsupported on MSVC2012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208388 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 02:26:36 +00:00
Saleem Abdulrasool
74d614a6fc ARM: support PIC on Windows on ARM
Handle lowering of global addresses for PIC mode compilation on Windows.  Always
use the movw/movt load to load the address as Windows on ARM requires ARMv7+ and
is a pure Thumb environment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208385 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 00:58:32 +00:00
Nick Lewycky
e584911870 printCustom is only used in PseudoSourceValue, remove it from Value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208383 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 00:49:03 +00:00
Rafael Espindola
9834b9001c Add missing linkage predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208379 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 00:36:18 +00:00
Lang Hames
7e2946b4e8 [RuntimeDyld] Unify the RuntimeDyldMachO resolve.*Relocation method signatures
around RelocationEntries, rather than passing the same information via loose
arguments.

No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208375 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 00:11:18 +00:00
Filipe Cabecinhas
e4a3254c02 Optimize shufflevector that copies an i64/f64 and zeros the rest.
Summary:
Also ran clang-format on the function. The code added is the last else
if block.

Reviewers: nadav, craig.topper, delena

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208372 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 23:16:08 +00:00
Quentin Colombet
8d53407abb [TargetInstrInfo] Fix the implementation of commuteInstruction to match the
comment of the API.

Relaxes the behavior of TargetInstrInfo::commuteInstruction when
TargetInstrInfo::findCommutedOpIndices returns false.

Previously TargetInstrInfo triggered a fatal error in such situation whereas based
on the comment in the API it should just return nullptr. Indeed the only
precondition that should be ensured is that the instruction must be commutable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208371 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 23:12:27 +00:00
Nick Lewycky
8ec421c255 Improve wording to make it sounds more like a change than an analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208370 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 23:04:46 +00:00
Justin Bogner
73773ce844 test/CodeGen: Check that the correct register is used in a store
This tightens up r208351 to ensure that a store is fed with the
correct value.

Thanks to Quentin Colombet for spotting this!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208368 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 22:45:07 +00:00
David Blaikie
bccff0f82d Reapply r207876 (Try simplifying LexicalScopes ownership again) including a workaround for an MSVC2012 bug regarding forward_as_tuple
(r207876 was reverted in r208131 after seeing some consistent buildbot
failure for MSVC 2012. The original commits were in r207724-r207726)

Takumi was nice enough to dig into this and locate this Microsoft
Connect issue:
http://connect.microsoft.com/VisualStudio/feedback/details/814899/forward-as-tuple-debug-implementation-error
describing a bug in MSVC2012's forward_as_tuple implementation.

Since the parameters in this instance are trivial/small, pass them by
value (using make_tuple) instead of perfectly-forwarded tuple of rvalue
references (involving the broken forward_as_tuple). Hopefully this will
satisfy MSVC2012.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208364 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 22:24:51 +00:00
David Blaikie
50f8a53856 Missed formatting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208362 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 21:53:33 +00:00
David Blaikie
2b94fa799b StringMap: Move assignment and move construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208361 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 21:52:29 +00:00
David Blaikie
06eb84e21a StringMap: Replace faux-copyability with faux-movability, which is sufficient.
This behavior was added to support StringMaps of StringMaps, default +
move construction are sufficient for this.

Real move construction support coming soon (& probably copy construction
too).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208360 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 21:52:26 +00:00
David Blaikie
b0439e6d6a StringMap support for move-only values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208359 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 21:52:23 +00:00
Tobias Grosser
24ac5dfba0 Correct formatting.
Sorry for the commit spam. My clang-format crashed on me and the vim
plugin did not print an error, but instead just left the formatting
untouched.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208358 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 21:43:19 +00:00
Tobias Grosser
3a722581b9 Use std::remove_if to remove elements from a vector
Suggested-by: Benjamin Kramer <benny.kra@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208357 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 21:32:59 +00:00
Michael Zolotukhin
6cc3e0e4e7 [InstCombine] Some cleanup in optimization of redundant insertvalue instructions.
And one more test added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208355 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 19:50:24 +00:00
Rafael Espindola
82cb28e99a Use range loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208353 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 19:30:17 +00:00
Justin Bogner
8115f93cdb Make a CodeGen test more robust against vector register selection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208351 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 18:53:56 +00:00
Jyotsna Verma
798f57f9c9 [Hexagon] Add new InstrItinClass to support timing classes.
This patch doesn't introduce any functionality change. Test cases will be
added later when v5 support is added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208349 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 18:47:08 +00:00
Rafael Espindola
5fd4b41a36 Use for range loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208348 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 18:40:06 +00:00
Sebastian Pop
dd2dc5b166 add testcase for r208237: do not collect undef terms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208347 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 18:38:58 +00:00
Rafael Espindola
e4b1c81995 Use range loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208346 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 18:17:44 +00:00
Matt Arsenault
459ff08eaa R600: Promote f64 vector load/stores to i64 for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208344 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 18:01:56 +00:00
Rafael Espindola
2413bf3004 Use a range loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208343 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 17:57:50 +00:00
Andrea Di Biagio
2360e51fd0 [X86] Add target specific combine rules to fold SSE2/AVX2 packed arithmetic shift intrinsics.
This patch teaches the backend how to combine packed SSE2/AVX2 arithmetic shift
intrinsics.

The rules are:
 - Always fold a packed arithmetic shift by zero to its first operand;
 - Convert a packed arithmetic shift intrinsic dag node into a ISD::SRA only if
   the shift count is known to be smaller than the vector element size.

This patch also teaches to function 'getTargetVShiftByConstNode' how fold
target specific vector shifts by zero.

Added two new tests to verify that the DAGCombiner is able to fold
sequences of SSE2/AVX2 packed arithmetic shift calls.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208342 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 17:44:04 +00:00
Saleem Abdulrasool
f37151a2fd test: fix test on Windows
When building on Windows, the default target is Windows.  Windows on ARM does
not support ARM mode compilation, resulting in test failures.  Simply specify a
triple to ensure that we are testing the correct behaviour.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208340 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 17:11:29 +00:00
NAKAMURA Takumi
cb64c55ba4 Mark test/TableGen/listconcat.td as XFAIL:vg_leak. llvm-tblgen is ignorant of vg_leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208337 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 17:06:10 +00:00
Daniel Sanders
d41a985f33 [mips] Add PredicateControl to InstAlias's
Summary:
No functional change

Depends on D3649

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3672

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208334 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 16:12:31 +00:00