Commit Graph

2224 Commits

Author SHA1 Message Date
Johnny Chen
c0b5dce3fa Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm,
instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98285 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11 21:02:50 +00:00
Bill Wendling
52a50e5d0e When outputing a non-lazy pointer for a stub, we may need to fill in the value
for the NLP because the object it's pointing to may be internal to the file.

This seems counter-intuitive, but bear with me. When we place the LSDA into the
TEXT section, the type info pointers need to be indirect and pc-rel. We
accomplish this by using NLPs. However, sometimes the types are local to the
file. GCC gets around this by not using a NLP in this case, but a "regular"
indirection like this:

GCC_except_tbl:
  .long Lfoo-.

__ZTIA:  @ This is local
  ...

Lfoo:
  .long __ZTIA

LLVM prefers NLPs on Darwin. In fact, it's more optimal for load performance to
use them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11 01:18:13 +00:00
Johnny Chen
ae1757b452 Added Thumb2 LDRD/STRD pre/post variants for disassembly only.
Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11 01:13:36 +00:00
Bob Wilson
5265a12f53 Fix ARM buildbot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11 00:46:22 +00:00
Bob Wilson
4d6113ee06 Lower small memcpys to load/stores on Thumb2.
Radar 7686922.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98210 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11 00:20:49 +00:00
Bob Wilson
fbacc888ee Fix an obvious typo in an assert.
Patch by Sean Callanan.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 22:38:45 +00:00
Bill Wendling
cebae36f57 Add a bit along with the MCSymbols stored in the MachineModuleInfo maps that
indicates that an MCSymbol is external or not. (It's true if it's external.)
This will be used to specify the correct information to add to non-lazy
pointers. That will be explained further when this bit is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 22:34:10 +00:00
Jim Grosbach
f49be7c96f Make sure the LR gets pushed in functions that use vaargs. This fixes
400.perlbench for the nightly tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 20:01:30 +00:00
Jim Grosbach
004453e85e comment why we use custom epilogue for t1 functions using vaargs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 19:59:47 +00:00
Johnny Chen
dd0f3cf189 Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 18:59:38 +00:00
Chris Lattner
98cdab53c3 set the temporary bit on MCSymbols correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 02:25:11 +00:00
Jim Grosbach
7c617b5e53 Clear up the last (famous last words) frame index value reuse issues for Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 00:13:42 +00:00
Jim Grosbach
dff4b4c5a7 Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 21:45:49 +00:00
Johnny Chen
a2c618a0f0 MSR (Move to Special Register from ARM core register) requires a mask to specify
what fields of the CPSR or SPSR are affected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98085 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 21:39:34 +00:00
Jim Grosbach
4e501545cd scavenged frame index value re-use gets confused when more than one base
register is involved for thumb1. Work around this for the moment by only
re-using SP-relative offsets. This is temporary 'til the code can distinguish
multiple base registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 19:07:28 +00:00
Bill Wendling
bdc38e5aa2 The ARM EH experiment worked!
Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 18:31:07 +00:00
Bill Wendling
94a1c631db This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please
bear with the awful code. It won't last in its current state beyond tonight.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 02:46:12 +00:00
Bill Wendling
cf6f28d84a Print blank line and clear stubs vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98019 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 00:43:34 +00:00
Bill Wendling
becd83e3f4 MC-ize the stub printing in ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 00:40:17 +00:00
Chris Lattner
82f05078b0 don't reset defaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98004 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 23:18:21 +00:00
Bob Wilson
f5fd499791 Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand.  We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 22:56:15 +00:00
Chris Lattner
d10a53d5a1 fix a bunch of partially ambiguous patterns on ARM. As an
example, this:

(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))

is ambiguous because DPR contains both f64 and v2f32.  tblgen
currently accidentally picks f64 because it's first in the 
regclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 18:51:21 +00:00
Anton Korobeynikov
ce7bf1c55f Initial bits of ARMv4-only support.
Patch by John Tytgat!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-06 19:39:36 +00:00
Jim Grosbach
e68bd74245 Thumb1 epilogue code generation needs to take into account that callee-saved
registers may be restored via a pop instruction, not just a tRestore.
This fixes nightly test 471.omnetep for Thumb1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-06 03:28:39 +00:00
Johnny Chen
fb86d78a45 Trivial comment change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-05 01:45:46 +00:00
Johnny Chen
267124cff2 Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 22:24:41 +00:00
Bob Wilson
436e6e7b5c pr6478: The frame pointer spill frame index is only defined when there is a
frame pointer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 21:42:36 +00:00
Bob Wilson
bbf39b0fd9 pr6480: Don't try producing ld/st-multiple instructions when the address is
an undef value.  This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at undefined addresses -- so it's not
worth the effort of doing anything more aggressive.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 21:04:38 +00:00
Johnny Chen
0635fc5c27 Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload
Instruction (PLI) for disassembly only.

According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"].  The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 17:40:44 +00:00
Johnny Chen
cb721da4c6 Modified the asm string of 16-bit Thumb MUL instruction so that it prints:
MULS <Rdm>, <Rn>, <Rdm>

according to A8.6.105 MUL Encoding T1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97675 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 23:15:43 +00:00
Johnny Chen
e54a3ef087 Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,
and STRHT for disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 18:45:36 +00:00
Johnny Chen
0f7866e796 Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG
for disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 02:09:43 +00:00
Evan Cheng
506049f29f - Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 01:44:33 +00:00
Evan Cheng
bc9d22c99a Eliminate unused instruction classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 00:43:15 +00:00
Johnny Chen
a43398283d Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for
disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97614 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 00:16:28 +00:00
Johnny Chen
10a77e14a0 Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97595 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 22:11:06 +00:00
Johnny Chen
b5031ad4c0 Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 19:38:59 +00:00
Johnny Chen
93042d1dc8 Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
Johnny Chen
9d3acaa1a0 AL is an optional mnemonic extension for always, except in IT instructions.
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.

Ref: A8.3 Conditional execution

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 17:57:15 +00:00
Johnny Chen
7cfa51ebd8 Change some asm shift opcode strings to lowercase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 17:03:18 +00:00
Xerxes Ranby
901a8b7c6b fix typo add missing (
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97565 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 13:42:03 +00:00
Xerxes Ranby
02735c97fd Unbreak llvm-arm-linux buildbot and fix PR5309.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97564 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 13:26:18 +00:00
Chris Lattner
7c306da505 Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 06:34:30 +00:00
Eric Christopher
8d17882efa Only save vector registers if we've defined for the vector registers.
Fixes PR5309.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97554 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 06:25:00 +00:00
Bill Wendling
46ada19645 Remove dead parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 01:55:18 +00:00
Johnny Chen
ad4df4c0da Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W
bit should be set to 0 instead of 1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 19:22:00 +00:00
Dan Gohman
bc9d98b52d The mayHaveSideEffects flag is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27 23:47:46 +00:00
Johnny Chen
adc7733a64 Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
Johnny Chen
6341c5a4c4 Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
and SRS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 20:25:24 +00:00
Johnny Chen
ce6275fd2c Added the 32-bit Thumb instructions (BXJ) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 19:05:29 +00:00