Benjamin Kramer
c21b205f93
InstCombine: Turn mul.with.overflow(X, 2) into the cheaper add.with.overflow(X, X)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131789 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-21 09:22:06 +00:00
Dan Gohman
424b777171
When BasicAA can determine that two pointers have the same base but
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differ by a dynamic offset, return PartialAlias instead of MayAlias.
See the comment in the code for details. This fixes PR9971.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-21 01:05:08 +00:00
Eli Friedman
c088345f13
Add fast-isel support for byval calls on x86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131764 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 22:21:04 +00:00
Rafael Espindola
b8adb8af0f
adds some attributes to attribute section when cpu is "xscale"
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(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 20:10:34 +00:00
Rafael Espindola
298c8e12ea
fixes target address tBL and tBLX and sets relocation type
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of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 20:01:01 +00:00
Stuart Hastings
0e29ed081b
Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.
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rdar://problem/8614450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 19:04:40 +00:00
Akira Hatanaka
17a1e87751
Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle
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saving and restoring them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131745 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 18:39:33 +00:00
Chad Rosier
5def9657e4
Fixed regression due to commit 131709, which disables vararg tail call optimizations on Win64
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131740 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 17:49:39 +00:00
Benjamin Kramer
eb274e6bdd
Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131730 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 15:11:26 +00:00
Cameron Zwarich
21a70bf4a5
Fix PR9960 by teaching SimpleRegisterCoalescing::AdjustCopiesBackFrom() to preserve
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the phikill flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131717 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 03:54:04 +00:00
Akira Hatanaka
cd0f90f831
Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 02:30:51 +00:00
Chad Rosier
a166089f36
Don't attempt to tail call optimize for Win64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 00:59:28 +00:00
Evan Cheng
2e6496026f
Revert r131664 and fix it in instcombine instead. rdar://9467055
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 00:54:37 +00:00
Eli Friedman
dc51575a5f
Add fast-isel support for zeroext and signext ret instructions on x86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 22:16:13 +00:00
Rafael Espindola
78ff647e44
Looks like OS X assemblers (including MC) don't like
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foo:
bar = foo
.quad bar
Avoid producing it. Fixes PR9951.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131687 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 22:05:56 +00:00
Eric Christopher
2bbecd8f6d
Oddly people want to use the 'r' constraint for fp constants on x86.
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Fixes rdar://9218925
Fixes PR9601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 21:33:47 +00:00
Eli Friedman
24a69c7be2
Fix up this test to use explicit triples (Win64 passes a different number of arguments in registers).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131676 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 21:13:08 +00:00
Jason W Kim
861b9c6a39
This fixes one divergence between LLVM and binutils for ARM in the
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text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:55:25 +00:00
Rafael Espindola
a3bff99f0a
ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
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Fixes PR9934.
We really need to start tblgening the relocation info :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:32:34 +00:00
Akira Hatanaka
a1a7ba8382
Align i64 arguments to 64 bit boundaries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:29:48 +00:00
Evan Cheng
0efaa5e6a1
crc32 with 64-bit output zeros upper 32-bits. rdar://9467055
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 18:57:12 +00:00
Stuart Hastings
26847d40db
Move test to Transforms/InstCombine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 05:53:22 +00:00
Rafael Espindola
cf227d5ad9
Add test for PR9946.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 02:35:26 +00:00
Eli Friedman
e6f364b6c4
More instcombine cleanup, towards improving debug line info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131604 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 23:58:37 +00:00
Tanya Lattner
db28247522
Handle perfect shuffle case that generates a vrev for vectors of floats.
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Add test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 21:44:54 +00:00
Dan Gohman
673968ae78
When forming an ICmpZero LSRUse, normalize the non-IV operand
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of the comparison, so that the resulting expression is fully
normalized. This fixes PR9939.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 21:02:18 +00:00
Johnny Chen
a96581f4f7
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 20:32:41 +00:00
Chad Rosier
871f664093
Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 19:59:50 +00:00
Eli Friedman
59f15918c2
More instcombine cleanup aimed towards improving debug line info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 19:57:14 +00:00
Stuart Hastings
1f2cb9824d
An imminent fix to the x86_64 byval logic will expose a flaw in the
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x86_64 sibcall logic. I've filed PR9943 for the sibcall problem, and
this patch alters the testcase to work around the flaw. When PR9943
is fixed, this patch should be reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 19:19:17 +00:00
Eli Friedman
5ceb66692e
Force a triple on a couple of tests; we don't support fast-isel of ret on Win64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131540 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 17:16:37 +00:00
Stuart Hastings
11d26f109d
Merge pmovzx test case into existing file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131539 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 17:02:04 +00:00
Justin Holewinski
657d1bed23
PTX: add flag to disable mad/fma selection
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Patch by Dan Bailey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 15:42:23 +00:00
Duncan Sands
bb1695e333
Tighten up checking of the validity of casts. (1) The IR parser would
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happily accept things like "sext <2 x i32> to <999 x i64>". It would
also accept "sext <2 x i32> to i64", though the verifier would catch
that later. Fixed by having castIsValid check that vector lengths match
except when doing a bitcast. (2) When creating a cast instruction, check
that the cast is valid (this was already done when creating constexpr
casts). While there, replace getScalarSizeInBits (used to allow more
vector casts) with getPrimitiveSizeInBits in getCastOpcode and isCastable
since vector to vector casts are now handled explicitly by passing to the
element types; i.e. this bit should result in no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 09:21:57 +00:00
Tanya Lattner
2a8eb722c7
In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
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Updated test case and reverted change to the PerfectShuffle Table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 06:42:21 +00:00
Eli Friedman
ef819d0ed8
Start trying to make InstCombine preserve more debug info. The idea here is to set the debug location on the IRBuilder, which will be then right location in most cases. This should magically give many transformations debug locations, and fixing places which are missing a debug location will usually just means changing the code creating it to use the IRBuilder.
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As an example, the change to InstCombineCalls catches a common case where a call to a bitcast of a function is rewritten.
Chris, does this approach look reasonable?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 01:28:27 +00:00
Eli Friedman
28b42afcb8
Make some of the fast-isel tests actually test fast-isel (and fix test failures).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 00:00:10 +00:00
Stuart Hastings
ca1ef48585
X86 pmovsx/pmovzx ignore the upper half of their inputs.
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rdar://problem/6945110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131493 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 22:13:31 +00:00
Tanya Lattner
c81c9709ef
vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 20:48:40 +00:00
Galina Kistanova
416b7117b7
Move test for appropriate directory.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 19:06:43 +00:00
Eli Friedman
19515b4e52
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
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This is r131438 with a couple small fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131474 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 18:29:03 +00:00
Stuart Hastings
71753050b1
Drop lli, revise test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131452 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 02:38:59 +00:00
Eli Friedman
c93943b6fe
Back out r131444 and r131438; they're breaking nightly tests. I'll look into
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it more tomorrow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 02:36:59 +00:00
Eli Friedman
b70eac42e7
Fix test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 00:39:14 +00:00
Evan Cheng
50ecb195e1
Add target triple so test doesn't fail on Windows machines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 00:15:58 +00:00
Eli Friedman
cdc9a20561
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 00:13:47 +00:00
Jakob Stoklund Olesen
f5497fb1b4
Teach LiveInterval::isZeroLength about null SlotIndexes.
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When instructions are deleted, they leave tombstone SlotIndex entries.
The isZeroLength method should ignore these null indexes.
This causes RABasic to sometimes spill a callee-saved register in the
abi-isel.ll test, so don't run that test with -regalloc=basic. Prioritizing
register allocation according to spill weight can cause more registers to be
used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131436 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 23:50:05 +00:00
Eli Friedman
57f4b03621
Remove dead code. Fix associated test to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 21:28:22 +00:00
Eli Friedman
482feb33b2
Make fast-isel work correctly s/uadd.with.overflow intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 21:06:17 +00:00
Eli Friedman
2586b8f936
Basic fast-isel of extractvalue. Not too helpful on its own, given the IR clang generates for cases like this, but it should become more useful soon.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131417 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 20:27:46 +00:00